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| r01ds0011ej0100 rev.1.00 page 1 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group renesas mcu datasheet 1. overview 1.1 features the r8c/la3a group, r8c/la5a group, r8c/la6a group, and r8c/LA8A group of single-chip mcus incorporate the r8c cpu core, which implements a powerful instruction set for a high level of efficiency and supports a 1 mbyte address space, allowing execution of instructions at high speed. in addition, the cpu core integrates a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus are designed to maximize emi/ems performance. integration of many peripheral functions, including mult ifunction timer and serial interface, helps reduce the number of system components. the r8c/la3a group, r8c/la5a group, r8c/la6a group, and r8c/LA8A group have data flash (1 kb 2 blocks). 1.1.1 applications household appliances, office equipment, au dio equipment, consumer products, etc. r01ds0011ej0100 rev.1.00 dec 21, 2010
r01ds0011ej0100 rev.1.00 page 2 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview 1.1.2 differences between groups table 1.1 lists the differences between groups, tables 1.2 and 1.3 list the programmable i/o ports provided for each group, and tables 1.4 and 1.5 list the lcd display function pins provided for each group. figures 1.9 to 1.12 show the pin assignment for each gr oup, and tables 1.9 to 1. 12 list product information. the explanations in the chapters which follow apply to the r8c/LA8A group only. note the differences shown below. note: 1. i/o ports are shared with i/o functi ons, such as interrupts or timers. refer to tables 1.13 to 1.17, pin name information by pin number, for details. table 1.1 differences between groups item function r8c/la3a group r8c/la5a group r8c/la6a group r8c/LA8A group i/o ports programmable i/o ports 26 pins 44 pins 56 pins 72 pins high current drive ports 8 pins 8 pins 8 pins 10 pins interrupts int interrupt pins 5 pins 6 pins 8 pins 8 pins timer rj timer rj0 output pin none none none 1 pin timer rj1 output pin none none none 1 pin timer rj2 i/o pin none none none 1 pin timer rj2 output pin none none none 1 pin timer rh timer rh output pin none 1 pin 1 pin 1 pin serial interface uart2 none none 1 pin 1 pin a/d converter analog input pins 5 pins 7 pins 8 pins 12 pins lcd drive control circuit segment output pins max. 11 pins max. 27 pins max. 32 pins max. 40 pins comparator b analog input voltage 1 pin 2 pins 2 pins 2 pins reference input voltage 1 pin 2 pins 2 pins 2 pins clock xcin pin shared with xin pin dedicated pin dedicated pin dedicated pin xcout pin shared with xout pin dedicated pin dedicated pin dedicated pin packages 32-pin lqfp 52-pin lqfp 64-pin lqfp 80-pin lqfp r01ds0011ej0100 rev.1.00 page 3 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview notes: 1. the symbol ? 3 ? indicates a programmable i/o port. 2. the symbol ??? indicates the settings should be made as follows: - set 0 to the corresponding bits in the pdi (i = 0, 3, 5, 7, 9) register. when read, the content is 0. - set 0 to the corresponding bits in the pi (i = 0, 3, 5, 7, 9) register. when read, the content is 0. notes: 1. the symbol ? 3 ? indicates a programmable i/o port. 2. the symbol ??? indicates the settings should be made as follows: - set 0 to the corresponding bits in the pdi (i = 1, 4 to 7, 9) register. when read, the content is 0. - set 0 to the corresponding bits in the pi (i = 1, 4 to 7, 9) register. when read, the content is 0. - set 0 to the corresponding bits in the p7drr register. when read, the content is 0. table 1.2 programmable i/o ports provided for each group (r8c/la3a group, r8c/la5a group) programmable i/o port r8c/la3a group total: 26 i/o pins r8c/la5a group total: 44 i/o pins bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 p0 ???????? 3 3 3 3 3 3 3 3 p2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p3 ???????? 3 3 3 3 3 3 3 3 p5 ? 3 3 3 3 3 3 3 ? 3 3 3 3 3 3 3 p7 ?????? 3 ?????? 3 3 3 p8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p9 ?????? 3 3 ?????? 3 3 table 1.3 programmable i/o ports provided for each group (r8c/la6a group, r8c/LA8A group) programmable i/o port r8c/la6a group total: 56 i/o pins r8c/LA8A group total: 72 i/o pins bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 p0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p1 3 3 3 3 3 3 ?? 3 3 3 3 3 3 3 3 p2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p4 3 3 ?????? 3 3 3 3 3 3 3 3 p5 ? 3 3 3 3 3 3 3 ? 3 3 3 3 3 3 3 p6 3 3 3 3 3 3 3 ? 3 3 3 3 3 3 3 3 p7 ????????? 3 3 3 3 3 3 3 p8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p9 ?????? 3 3 ?????? 3 3 r01ds0011ej0100 rev.1.00 page 4 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview notes: 1. the symbol ??? indicates there is no lcd display functi on. set the corresponding bits to 0 by setting registers lse0, lse2, and lse5 for these pins. 2. when using the lcd drive control circuit, set t he corresponding bit in the lse5 register to 1. notes: 1. the symbol ??? indicates there is no lcd display functi on. set the corresponding bits to 0 by setting registers lse1, lse4 and lse5 for these pins. 2. when using the lcd drive control circuit, set t he corresponding bit in the lse5 register to 1. table 1.4 lcd display function pins provided for each group (r8c/la3a group, r8c/la5a group) shared i/o port r8c/la3a group common output: max. 4 segment output: max. 11 r8c/la5a group common output: max. 4 segment output: max. 27 p0 ???????? seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 p2 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 p3 ???????? seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 p5 ? vl3 (2) vl2 (2) vl1 (2) com 0 com 1 seg 26 com 2 seg 25 com 3 seg 24 ? vl3 (2) vl2 (2) vl1 (2) com 0 com 1 seg 26 com 2 seg 25 com 3 seg 24 table 1.5 lcd display function pins provided for each group (r8c/la6a group, r8c/LA8A group) shared i/o port r8c/la6a group common output: max. 4 segment output: max. 32 r8c/LA8A group common output: max. 4 segment output: max. 40 p0 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 p1 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 ?? seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 p2 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 p3 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 p4 seg 39 seg 38 ?????? seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 p5 ? vl3 (2) vl2 (2) vl1 (2) com 0 com 1 com 2 com 3 ? vl3 (2) vl2 (2) vl1 (2) com 0 com 1 com 2 com 3 r01ds0011ej0100 rev.1.00 page 5 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview 1.1.3 specifications tables 1.6 to 1.8 list the specifications. note: 1. no pull-up resistor is provided in the pins p5_4 to p5_6. table 1.6 specifications (1) item function specification cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 2.7 v to 5.5 v) 125 ns (f(xin) = 8 mhz, vcc = 1.8 v to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom/ram data flash refer to tables 1.9 to 1.12 product lists. power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) i/o ports programmable i/o ports r8c/la3a group ? cmos i/o ports: 26, selectable pull-up resistor (1) ? high current drive ports: 8 r8c/la5a group ? cmos i/o ports: 44, selectable pull-up resistor (1) ? high current drive ports: 8 r8c/la6a group ? cmos i/o ports: 56, selectable pull-up resistor (1) ? high current drive ports: 8 r8c/LA8A group ? cmos i/o ports: 72, selectable pull-up resistor (1) ? high current drive ports: 10 clock clock generation circuits 4 circui ts: xin clock oscillation circuit xcin clock oscillation circuit (32 khz) high-speed on-chip oscillator (with frequency adjustment function) low-speed on-chip oscillator ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: division ratio selectable from 1, 2, 4, 8, and 16 ? low-power-consumption modes: standard operating mode (high-speed clock, low-speed clock, high- speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode, power-off mode real-time clock (timer rh) interrupts r8c/la3a group ? num ber of interrupt vectors: 69 ? external interrupt: 13 (int 5, key input 8) ? priority levels: 7 levels r8c/la5a group ? number of interrupt vectors: 69 ? external interrupt: 14 (int 6, key input 8) ? priority levels: 7 levels r8c/la6a group ? number of interrupt vectors: 69 ? external interrupt: 16 (int 8, key input 8) ? priority levels: 7 levels r8c/LA8A group watchdog timer ? 14 bits 1 (with prescaler) ? selectable reset start function ? selectable low-speed on-chip oscillator for watchdog timer r01ds0011ej0100 rev.1.00 page 6 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview table 1.7 specifications (2) item function specification timer timer rb0, timer rb1 8 bits 2 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) timer rh real-time clock mode (counting of seconds, minutes, hours, day of the week, date, month, year), output compare mode timer rj0 timer rj1 timer rj2 r8c/la3a group timer rj0, timer rj1 16 bits 2 timer mode (perio d timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode r8c/la5a group r8c/la6a group r8c/LA8A group timer rj0, timer rj1, timer rj2 16 bits 3 serial interface uart0 1 channel clock synchronous serial i/o/uart uart2 1 channel clock synchronous serial i/o/uart, i 2 c mode (i 2 c-bus), multiprocessor communication function synchronous serial communication unit (ssu) 1 (shared with i 2 c-bus) i 2 c bus 1 (shared with ssu) a/d converter r8c/la3a group 10-bit resolution 5 channels, including sample and hold function, with sweep mode, temperature sensor included (measurement temperature range: ? 20 to 85 c (n version)/ ? 40 to 85 c (d version)) r8c/la5a group 10-bit resolution 7 channels, including sample and hold function, with sweep mode, temperature sensor included (measurement temperature range: ? 20 to 85 c (n version)/ ? 40 to 85 c (d version)) r8c/la6a group 10-bit resolution 8 channels, including sample and hold function, with sweep mode, temperature sensor included (measurement temperature range: ? 20 to 85 c (n version)/ ? 40 to 85 c (d version)) r8c/LA8A group 10-bit resolution 12 channels, including sample and hold function, with sweep mode, temperature sensor included (measurement temperature range: ? 20 to 85 c (n version)/ ? 40 to 85 c (d version)) comparator b r8c/la3a group 1 circuit (comparator b1) r8c/la5a group 2 circuits (comparator b1, comparator b3) r8c/la6a group r8c/LA8A group r01ds0011ej0100 rev.1.00 page 7 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview note: 1. specify the d version if d ve rsion functions are to be used. table 1.8 specifications (3) item function specification lcd drive control circuit r8c/la3a group common output: max. 4 pins segment output: max. 11 pins ? bias: 1/2, 1/3 ? duty: static, 1/2, 1/3, 1/4 r8c/la5a group common output: max. 4 pins segment output: max. 27 pins r8c/la6a group common output: max. 4 pins segment output: max. 32 pins r8c/LA8A group common output: max. 4 pins segment output: max. 40 pins flash memory ? programming and erasure voltage: vcc = 1.8 v to 5.5 v (data flash vcc = 1.8 v to 5.5 v) ? programming and erasure endur ance: 10,000 times (data flash) 10,000 times (program rom) ? program security: rom code protect, id code check ? on-chip debug function ? on-board flash rewrite function operating frequency/ supply voltage f(xin) = 20 mhz (vcc = 2.7 v to 5.5 v) f(xin) = 8 mhz (vcc = 1.8 v to 5.5 v) current consumption typ. 4.7 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 2.3 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 1.7 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz)) typ. 0.5 a (vcc = 3.0 v, stop mode) typ. 1.3 a (vcc = 3.0 v, power-off 2 mode, timer rh enabled) typ. 0.01 a (vcc = 3.0 v, power-off 0 mode, timer rh disabled) operating ambient temperature ? 20 to 85 c (n version) ? 40 to 85 c (d version) (1) r01ds0011ej0100 rev.1.00 page 8 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview 1.2 product lists tables 1.9 to 1.12 list product informat ion for each group. fi gures 1.1 to 1.4 show the correspondence of part no., with memory size and package for each group. table 1.9 product list for r8c/la3a group current of dec 2010 figure 1.1 correspondence of part no., with memory size and package of r8c/la3a group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2la32anfp 8 kbytes 1 kbyte 2 2 kbytes plqp0032gb-a n version r5f2la34anfp 16 kbytes 1 kbyte 2 2 kbytes plqp0032gb-a r5f2la36anfp 32 kbytes 1 kbyte 2 2 kbytes plqp0032gb-a r5f2la38anfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0032gb-a r5f2la32adfp 8 kbytes 1 kbyte 2 2 kbytes plqp0032gb-a d version r5f2la34adfp 16 kbytes 1 kbyte 2 2 kbytes plqp0032gb-a r5f2la36adfp 32 kbytes 1 kbyte 2 2 kbytes plqp0032gb-a r5f2la38adfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0032gb-a part no. r 5 f 2l a3 8 a n fp package type: fp: lqfp (0.8 mm pin-pitch) classification n: operating ambient temperature ? 20 to 85c d: operating ambient temperature ? 40 to 85c dataflash a: dataflash rom capacity 2: 8kb 4: 16kb 6: 32kb 8: 64kb r8c/la3a group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r01ds0011ej0100 rev.1.00 page 9 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview table 1.10 product list for r8c/la5a group current of dec 2010 figure 1.2 correspondence of part no., with memory size and package of r8c/la5a group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2la52anfp 8 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a n version r5f2la54anfp 16 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f2la56anfp 32 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f2la58anfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0052ja-a r5f2la52adfp 8 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a d version r5f2la54adfp 16 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f2la56adfp 32 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f2la58adfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0052ja-a part no. r 5 f 2l a5 8 a n fp package type: fp: lqfp (0.65 mm pin-pitch) classification n: operating ambient temperature ? 20 to 85c d: operating ambient temperature ? 40 to 85c dataflash a: dataflash rom capacity 2: 8kb 4: 16kb 6: 32kb 8: 64kb r8c/la5a group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r01ds0011ej0100 rev.1.00 page 10 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview table 1.11 product list for r8c/la6a group current of dec 2010 figure 1.3 correspondence of part no., with memory size and package of r8c/la6a group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2la64anfp 16 kbytes 1 kbyte 2 2 kbytes plqp0064kb-a n version r5f2la64anfa 16 kbytes 1 kbyte 2 2 kbytes plqp0064ga-a r5f2la66anfp 32 kbytes 1 kbyte 2 2 kbytes plqp0064kb-a r5f2la66anfa 32 kbytes 1 kbyte 2 2 kbytes plqp0064ga-a r5f2la67anfp 48 kbytes 1 kbyte 2 3.5 kbytes plqp0064kb-a r5f2la67anfa 48 kbytes 1 kbyte 2 3.5 kbytes plqp0064ga-a r5f2la68anfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0064kb-a r5f2la68anfa 64 kbytes 1 kbyte 2 3.5 kbytes plqp0064ga-a r5f2la64adfp 16 kbytes 1 kbyte 2 2 kbytes plqp0064kb-a d version r5f2la64adfa 16 kbytes 1 kbyte 2 2 kbytes plqp0064ga-a r5f2la66adfp 32 kbytes 1 kbyte 2 2 kbytes plqp0064kb-a r5f2la66adfa 32 kbytes 1 kbyte 2 2 kbytes plqp0064ga-a r5f2la67adfp 48 kbytes 1 kbyte 2 3.5 kbytes plqp0064kb-a r5f2la67adfa 48 kbytes 1 kbyte 2 3.5 kbytes plqp0064ga-a r5f2la68adfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0064kb-a r5f2la68adfa 64 kbytes 1 kbyte 2 3.5 kbytes plqp0064ga-a part no. r 5 f 2l a6 8 a n fp package type: fp: lqfp (0.5 mm pin-pitch) fa: lqfp (0.8 mm pin-pitch) classification n: operating ambient temperature ? 20 to 85c d: operating ambient temperature ? 40 to 85c dataflash a: dataflash rom capacity 4: 16kb 6: 32kb 7: 48kb 8: 64kb r8c/la6a group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r01ds0011ej0100 rev.1.00 page 11 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview table 1.12 product list for r8c/LA8A group current of dec 2010 figure 1.4 correspondence of part no., with memory size and package of r8c/LA8A group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2la84anfp 16 kbytes 1 kbyte 2 2 kbytes plqp0080kb-a n version r5f2la84anfa 16 kbytes 1 kbyte 2 2 kbytes plqp0080ja-a r5f2la86anfp 32 kbytes 1 kbyte 2 2 kbytes plqp0080kb-a r5f2la86anfa 32 kbytes 1 kbyte 2 2 kbytes plqp0080ja-a r5f2la87anfp 48 kbytes 1 kbyte 2 3.5 kbytes plqp0080kb-a r5f2la87anfa 48 kbytes 1 kbyte 2 3.5 kbytes plqp0080ja-a r5f2la88anfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0080kb-a r5f2la88anfa 64 kbytes 1 kbyte 2 3.5 kbytes plqp0080ja-a r5f2la84adfp 16 kbytes 1 kbyte 2 2 kbytes plqp0080kb-a d version r5f2la84adfa 16 kbytes 1 kbyte 2 2 kbytes plqp0080ja-a r5f2la86adfp 32 kbytes 1 kbyte 2 2 kbytes plqp0080kb-a r5f2la86adfa 32 kbytes 1 kbyte 2 2 kbytes plqp0080ja-a r5f2la87adfp 48 kbytes 1 kbyte 2 3.5 kbytes plqp0080kb-a r5f2la87adfa 48 kbytes 1 kbyte 2 3.5 kbytes plqp0080ja-a r5f2la88adfp 64 kbytes 1 kbyte 2 3.5 kbytes plqp0080kb-a r5f2la88adfa 64 kbytes 1 kbyte 2 3.5 kbytes plqp0080ja-a part no. r 5 f 2l a8 8 a n fp package type: fp: lqfp (0.5 mm pin-pitch) fa: lqfp (0.65 mm pin-pitch) classification n: operating ambient temperature ? 20 to 85c d: operating ambient temperature ? 40 to 85c dataflash a: dataflash rom capacity 4: 16kb 6: 32kb 7: 48kb 8: 64kb r8c/LA8A group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r01ds0011ej0100 rev.1.00 page 12 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview 1.3 block diagrams figure 1.5 shows a block diagram of r8c/la3a group. figure 1.6 shows a block diagram of r8c/la5a group. figure 1.7 shows a block diagram of r8c/la6a group. figure 1.8 shows a block diagram of r8c/LA8A group. figure 1.5 block diagram of r8c/la3a group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer rb (8 bits 2) timer rc (16 bits 1) timer rh timer rj (16 bits 2) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports a/d converter (10 bits 5 channels) uart or clock synchronous serial i/o (8 bits 1) i 2 c bus or ssu (8 bits 1) rom (1) peripheral functions lcd drive control circuit common output: max. 4 pins segment output: max. 11 pins temperature sensor comparator b 1 ch notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. 2 port p9 8 port p8 1 port p7 port p5 7 port p2 8 voltage detection circuit low-speed on-chip oscillator for watchdog timer r01ds0011ej0100 rev.1.00 page 13 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview figure 1.6 block diagram of r8c/la5a group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer rb (8 bits 2) timer rc (16 bits 1) timer rh timer rj (16 bits 2) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports a/d converter (10 bits 7 channels) uart or clock synchronous serial i/o (8 bits 1) i 2 c bus or ssu (8 bits 1) rom (1) peripheral functions lcd drive control circuit common output: max. 4 pins segment output: max. 27 pins temperature sensor 8 port p8 2 port p9 3 port p7 comparator b 2 ch notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. port p0 8 port p2 8 port p3 8 port p5 7 voltage detection circuit low-speed on-chip oscillator for watchdog timer r01ds0011ej0100 rev.1.00 page 14 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview figure 1.7 block diagram of r8c/la6a group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer rb (8 bits 2) timer rc (16 bits 1) timer rh timer rj (16 bits 2) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports a/d converter (10 bits 8 channels) uart or clock synchronous serial i/o (8 bits 1) i 2 c bus or ssu (8 bits 1) 8 port p0 6 port p1 8 port p3 8 port p2 rom (1) peripheral functions lcd drive control circuit common output: max. 4 pins segment output: max. 32 pins temperature sensor 7 port p6 2 port p9 comparator b 2ch port p4 2 port p5 7 8 port p8 notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. uart, clock synchronous serial i/o, or i 2 c bus (8 bits 1) voltage detection circuit low-speed on-chip oscillator for watchdog timer r01ds0011ej0100 rev.1.00 page 15 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview figure 1.8 block diagram of r8c/LA8A group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer rb (8 bits 2) timer rc (16 bits 1) timer rh timer rj (16 bits 3) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports a/d converter (10 bits 12 channels) uart or clock synchronous serial i/o (8 bits 1) i 2 c bus or ssu (8 bits 1) uart, clock synchronous serial i/o, or i 2 c bus (8 bits 1) 8 port p0 8 port p1 8 port p3 7 port p5 port p4 8 port p2 rom (1) peripheral functions lcd drive control circuit common output: max. 4 pins segment output: max. 40 pins temperature sensor 8 port p6 8 port p8 2 port p9 7 port p7 8 comparator b 2ch notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. voltage detection circuit low-speed on-chip oscillator for watchdog timer r01ds0011ej0100 rev.1.00 page 16 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview 1.4 pin assignments figures 1.9 to 1.12 show pin assignments (top view). ta bles 1.13 to 1.17 list the pin name information by pin number. figure 1.9 pin assignment (top view) of plqp0032gb-a package p5_4/vl1 p5_3/com0/ki7 p5_2/com1/seg26/ki6 p5_5/vl2 p5_6/vl3 p8_0/ivcmp1/scs/int1 p8_7(/trctrg)/trcioa/ivref1/an3 p8_6(/trciob)/rxd0/an2 p2_7/seg15/comexp/ki3 p2_2/seg10/int0 p2_5/seg13(/int2)/ki1 p2_6/seg14(/int3)/ki2 p2_3/seg11/int5 p2_4/seg12(/int1)/ki0 p8_2/trj1io/ssck/scl p8_1/ssi/int3 p8_4/trciod(/trciob)/clk0/an0 wkup0 8 7 6 5 4 3 2 1 p2_1/seg9/trb0o p2_0/seg8/trb1o p7_1/trcclk/int2/an5 p8_5/trcioc(/trciob)/txd0/an1 reset vref mode p9_1/xout(/xcout) vss/avss p9_0/xin(/xcin) vcc/avcc p8_3/trj0io/sso/sda 12 13 14 15 16 11 10 9 17 18 19 20 21 22 23 24 29 28 27 26 25 30 31 32 r8c/la3a group plqp0032gb-a (32p6u-a) (top view) p5_1/com2/seg25/ki5 p5_0/com3/seg24/ki4 notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the packa ge by referring to the package dimensions. r01ds0011ej0100 rev.1.00 page 17 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview figure 1.10 pin assignment (top view) of plqp0052ja-a package p5_4/vl1 p5_3/com0/ki7 p5_2/com1/seg26/ki6 p5_1/com2/seg25/ki5 p5_0/com3/seg24/ki4 p5_5/vl2 p5_6/vl3 p8_0/ivcmp1/scs/int1 p0_0/seg0(/trctrg)/int7/adtrg p0_1/seg1 p0_2/seg2 p0_3/seg3/sso/sda p0_4/seg4/ssck/scl p0_5/seg5/ssi p0_6/seg6/scs p8_7(/trctrg)/trcioa/ivref1/an3 p2_7/seg15/comexp/ki3 p3_0/seg16 p3_4/seg20 p3_5/seg21 p3_6/seg22 p3_1/seg17 p3_2/seg18 p3_3/seg19 p2_2/seg10/int0 p2_5/seg13(/int2)/ki1 p2_6/seg14(/int3)/ki2 p3_7/seg23 p2_3/seg11/int5 p2_4/seg12(/int1)/ki0 p8_2/trj1io/ssck/scl p8_1/ivcmp3/ssi/int3 p8_5/trcioc(/trciob)/txd0/an1 p8_4/trciod(/trciob)/clk0/an0 reset wkup0 xcin xcout vref mode p9_1/xout vss/avss p9_0/xin vcc/avcc p8_3/trj0io/sso/sda 17 18 19 20 21 22 23 24 25 26 16 15 14 49 48 47 46 45 44 43 42 41 40 50 51 52 13 12 11 10 9 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 37 38 39 r8c/la5a group plqp0052ja-a (52p6a-a) (top view) p2_0/seg8/trb1o p2_1/seg9/trb0o p0_7/seg7/trho p8_6(/trciob)/rxd0/an2 p7_1/trcclk/int2/an5 p7_0/ivref3/wkup1/an4 p7_2(/trctrg)/an6 notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. r01ds0011ej0100 rev.1.00 page 18 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview note: 1. the pin in parentheses can be assigned by a program. 2. pins (xcout) and (xcin) are not available in the r8c/la5a group. 3. the ivcmp3 pin is not available in the r8c/la3a group. table 1.13 pin name information by pin number (r8c/la3a group, r8c/la5a group)(1) pin number control pin port i/o pin functions for peripheral modules la5a la3a interrupt timer serial interface ssu i 2 c bus a/d converter, comparator b lcd drive control circuit 1 30 p8_5 trcioc/ (trciob) txd0 an1 2 31 p8_4 trciod/ (trciob) clk0 an0 332 wkup0 4 1 vref 52 mode 6xcin 7xcout 83 reset 94 xout (xcout) (2) p9_1 10 5 vss/avss 11 6 xin (xcin) (2) p9_0 12 7 vcc/avcc 13 8 p8_3 trj0io sso sda 14 9 p8_2 trj1io ssck scl 15 10 p8_1 int3 ssi ivcmp3 (3) 16 11 p8_0 int1 scs ivcmp1 17 12 p5_6 vl3 18 13 p5_5 vl2 19 14 p5_4 vl1 20 15 p5_3 ki7 com0 21 16 p5_2 ki6 seg26/ com1 22 17 p5_1 ki5 seg25/ com2 23 18 p5_0 ki4 seg24/ com3 24 p3_7 seg23 25 p3_6 seg22 26 p3_5 seg21 27 p3_4 seg20 28 p3_3 seg19 29 p3_2 seg18 30 p3_1 seg17 r01ds0011ej0100 rev.1.00 page 19 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview note: 1. the pin in parentheses can be assigned by a program. table 1.14 pin name information by pin number (r8c/la3a group, r8c/la5a group)(2) pin number control pin port i/o pin functions for peripheral modules la5a la3a interrupt timer serial interface ssu i 2 c bus a/d converter, comparator b lcd drive control circuit 31 p3_0 seg16 32 19 p2_7 ki3 seg15/ comexp 33 20 p2_6 (int3 )/ki2 seg14 34 21 p2_5 (int2 )/ki1 seg13 35 22 p2_4 (int1 )/ki0 seg12 36 23 p2_3 int5 seg11 37 24 p2_2 int0 seg10 38 25 p2_1 trb0o seg9 39 26 p2_0 trb1o seg8 40 p0_7 trho seg7 41 p0_6 scs seg6 42 p0_5 ssi seg5 43 p0_4 ssck scl seg4 44 p0_3 sso sda seg3 45 p0_2 seg2 46 p0_1 seg1 47 p0_0 int7 (trctrg) adtrg seg0 48 p7_2 (trctrg) an6 49 27 p7_1 int2 trcclk an5 50 wkup1 p7_0 an4/ivref3 51 28 p8_7 trcioa/ (trctrg) an3/ivref1 52 29 p8_6 (trciob) rxd0 an2 r01ds0011ej0100 rev.1.00 page 20 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview figure 1.11 pin assignment (top view) of plqp0064kb-a and plqp0064ga-a packages 20 21 22 23 24 25 26 27 28 29 30 31 32 19 18 17 61 60 59 58 57 56 55 54 53 52 51 50 49 62 63 64 36 37 38 39 40 41 42 43 44 45 46 47 48 33 34 35 13 12 11 10 9 8 7 6 5 4 3 2 116 15 14 p1_7/seg15 p2_0/seg16 p2_4/seg20 p2_5/seg21 p2_6/seg22 p2_1/seg17 p2_2/seg18 p2_3/seg19 p1_2/seg10/ki6 p1_5/seg13/int5 p1_6/seg14/int6 p2_7/seg23 p3_0/seg24(/int0) p3_1/seg25(/int1) p1_3/seg11/ki7 p1_4/seg12/int4 plqp0064kb-a (64p6q-a) plqp0064ga-a (64p6u-a) (top view) r8c/la6a group p5_4/vl1 p5_3/com0 p5_2/com1 p5_1/com2 p5_0/com3 p4_7/seg39/comexp p4_6/seg38 p3_7/seg31(/int7) p3_6/seg30(/int6) p3_5/seg29(/int5) p3_4/seg28(/int4) p3_3/seg27(/int3) p3_2/seg26(/int2) p5_5/vl2 p5_6/vl3 p8_0/scs/ivcmp1/int1 p6_3(/ssck/scl)/an6 p6_4(/sso/sda)/an7 p6_5(/trciod/trciob)/ivref1(/trb1o)/an8 p6_6(/trcioc/trciob)/ivref3(/trb0o)/an9 p6_7(/trciob)/an10 p0_0/seg0(/trcioa/trctrg)/an11 p0_1/seg1/int7(/trcclk/trctrg)/adtrg p0_2/seg2(/trctrg)/ki0 p0_3/seg3/int0/ki1 p0_4/seg4/ki2 p0_5/seg5/ki3 p0_6/seg6/ki4 p0_7/seg7/trho/ki5 p6_2(/trj0io/ssi)/an5 p6_1(/trj1io/scs)/an4 p8_7/trb0o/int2(/cts2/rts2) reset p9_1/xout p8_6(/rxd0/rxd2/scl2) p8_5(/txd0/txd2/sda2) p8_4(/clk0/clk2) vss/avss p9_0/xin vcc/avcc wkup0 xcin xcout p8_3/sso/sda(/trj0io) p8_2/ssck/scl(/trj1io) p8_1/ssi/ivcmp3/int3 vref mode notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. r01ds0011ej0100 rev.1.00 page 21 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview figure 1.12 pin assignment (top view) of plqp0080kb-a and plqp0080ja-a packages 13 12 11 10 9 8 7 6 5 4 3 2 116 15 14 mode xcin vss/avss p9_0/xin vcc/avcc xcout reset p9_1/xout p7_1(/txd2/sda2/rxd2/scl2)/trj1o wkup0 vref p8_6(/rxd0/rxd2/scl2) p8_5(/txd0/txd2/sda2) p8_4(/clk0/clk2) p7_0(/clk2)/trj2o/wkup1 p8_7/trb0o/int2(/cts2/rts2) 17 20 19 18 p8_3/sso/sda(/trj0io) p8_2/ssck/scl(/trj1io) p8_1/ssi/ivcmp3/int3 p8_0/scs/ivcmp1/int1 28 29 30 31 32 33 34 35 36 37 38 39 40 27 26 25 p4_7/seg39/comexp p4_6/seg38 p4_4/seg36 p4_3/seg35 p4_2/seg34 p4_1/seg33 p4_0/seg32 p3_7/seg31(/int7) p3_6/seg30(/int6) p3_5/seg29(/int5) p3_4/seg28(/int4) p3_3/seg27(/int3) p5_0/com3 p5_1/com2 p5_2/com1 24 23 22 21 p5_3/com0 p5_4/vl1 p5_5/vl2 p5_6/vl3 p1_4/seg12/int4 p1_5/seg13/int5 p2_1/seg17 p2_2/seg18 p2_3/seg19 p1_6/seg14/int6 p1_7/seg15 p2_0/seg16 p0_7/seg7/trho/ki5 p1_2/seg10/ki6 p1_3/seg11/ki7 p2_4/seg20 p2_5/seg21 p2_6/seg22 p1_0/seg8 p1_1/seg9 48 49 50 51 52 53 54 55 56 57 58 59 60 45 46 47 44 41 42 43 p2_7/seg23 p3_0/seg24(/int0) p3_1/seg25(/int1) p3_2/seg26(/int2) 73 72 71 70 69 68 67 66 65 64 63 62 61 74 75 76 p6_2(/trj0io/ssi)/an5 p6_3(/ssck/scl)/an6 p6_4(/sso/sda)/an7 p6_5(/trciod/trciob)/ivref1(/trb1o)/an8 p6_6(/trcioc/trciob)/ivref3(/trb0o)/an9 p6_7(/trciob)/an10 p0_0/seg0(/trcioa/trctrg)/an11 p0_1/seg1/int7(/trcclk/trctrg)/adtrg p0_2/seg2(/trctrg)/ki0 p0_3/seg3/int0/ki1 p0_4/seg4/ki2 p0_5/seg5/ki3 p0_6/seg6/ki4 p6_1(/trj1io/scs)/an4 p6_0(/trj2io)/an3 p7_6(/trb0o)/an2 77 p7_5/trb1o/an1 78 p7_4/an0 79 p7_3(/cts2/rts2) 80 p7_2(/txd2/sda2/rxd2/scl2)/trj0o r8c/LA8A group plqp0080kb-a (80p6q-a) plqp0080ja-a (fp-80w/fp-80wv) (top view) p4_5/seg37 notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. r01ds0011ej0100 rev.1.00 page 22 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview note: 1. the pin in parentheses can be assigned by a program. table 1.15 pin name information by pin number (r8c/la6a group, r8c/LA8A group)(1) pin number control pin port i/o pin functions for peripheral modules LA8A la6a interrupt timer serial interface ssu i 2 c bus a/d converter, comparator b lcd drive control circuit 1 p7_1 trj1o (txd2/sda2/rxd2/ scl2) 2 wkup1 p7_0 trj2o (clk2) 3 64 p8_7 int2 trb0o (cts2 /rts2 ) 41 wkup0 5 2 vref 63mode 74xcin 8 5 xcout 96 reset 10 7 xout p9_1 11 8 vss/ avss 12 9 xin p9_0 13 10 vcc/ avcc 14 11 p8_6 (rxd0/rxd2/scl2) 15 12 p8_5 (txd0/txd2/sda2) 16 13 p8_4 (clk0/clk2) 17 14 p8_3 (trj0io) sso sda 18 15 p8_2 (trj1io) ssck scl 19 16 p8_1 int3 ssi ivcmp3 20 17 p8_0 int1 scs ivcmp1 21 18 p5_6 vl3 22 19 p5_5 vl2 23 20 p5_4 vl1 24 21 p5_3 com0 25 22 p5_2 com1 26 23 p5_1 com2 27 24 p5_0 com3 28 25 p4_7 seg39/ comexp 29 26 p4_6 seg38 30 p4_5 seg37 r01ds0011ej0100 rev.1.00 page 23 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview note: 1. the pin in parentheses can be assigned by a program. table 1.16 pin name information by pin number (r8c/la6a group, r8c/LA8A group)(2) pin number control pin port i/o pin functions for peripheral modules LA8A la6a interrupt timer serial interface ssu i 2 c bus a/d converter, comparator b lcd drive control circuit 31 p4_4 seg36 32 p4_3 seg35 33 p4_2 seg34 34 p4_1 seg33 35 p4_0 seg32 36 27 p3_7 (int7 ) seg31 37 28 p3_6 (int6 ) seg30 38 29 p3_5 (int5 ) seg29 39 30 p3_4 (int4 ) seg28 40 31 p3_3 (int3 ) seg27 41 32 p3_2 (int2 ) seg26 42 33 p3_1 (int1 ) seg25 43 34 p3_0 (int0 ) seg24 44 35 p2_7 seg23 45 36 p2_6 seg22 46 37 p2_5 seg21 47 38 p2_4 seg20 48 39 p2_3 seg19 49 40 p2_2 seg18 50 41 p2_1 seg17 51 42 p2_0 seg16 52 43 p1_7 seg15 53 44 p1_6 int6 seg14 54 45 p1_5 int5 seg13 55 46 p1_4 int4 seg12 56 47 p1_3 ki7 seg11 57 48 p1_2 ki6 seg10 58 p1_1 seg9 59 p1_0 seg8 60 49 p0_7 ki5 trho seg7 61 50 p0_6 ki4 seg6 62 51 p0_5 ki3 seg5 63 52 p0_4 ki2 seg4 64 53 p0_3 ki1 / int0 seg3 65 54 p0_2 ki0 (trctrg) seg2 66 55 p0_1 int7 (trctrg/ trcclk) adtrg seg1 67 56 p0_0 (trcioa/ trctrg) an11 seg0 68 57 p6_7 (trciob) an10 r01ds0011ej0100 rev.1.00 page 24 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview note: 1. the pin in parentheses can be assigned by a program. table 1.17 pin name information by pin number (r8c/la6a group, r8c/LA8A group)(3) pin number control pin port i/o pin functions for peripheral modules LA8A la6a interrupt timer serial interface ssu i 2 c bus a/d converter, comparator b lcd drive control circuit 69 58 p6_6 (trb0o/ trciob/ trcioc) an9/ivref3 70 59 p6_5 (trb1o/ trciob/ trciod) an8/ivref1 71 60 p6_4 (sso) (sda) an7 72 61 p6_3 (ssck) (scl) an6 73 62 p6_2 (trj0io) (ssi) an5 74 63 p6_1 (trj1io) (scs ) an4 75 p6_0 (trj2io) an3 76 p7_6 (trb0o) an2 77 p7_5 trb1o an1 78 p7_4 an0 79 p7_3 (cts2 /rts2 ) 80 p7_2 trj0o (rxd2/scl2/ txd2/sda2) r01ds0011ej0100 rev.1.00 page 25 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview 1.5 pin functions tables 1.18 and 1.19 list pin functions for r8c/la5a gro up, and tables 1.20 and 1.21 list pin functions for r8c/ LA8A group. i: input o: output i/o: input and output note: 1. contact the oscillator manufactur er for oscillation characteristics. table 1.18 pin functions for r8c/la5a group (1) item pin name i/o type description power supply input vcc, vss ? apply 1. 8 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i driving this pin low resets the mcu. mode mode i connect this pin to vcc via a resistor. power-off 0 mode exit input wkup0 i this pin is provided for input to exit the mode used in power-off 0 mode. connect to vss when not using power-off 0 mode. wkup1 i this pin is provided for input to exit the mode used in power-off 0 mode. xin clock input xin i these pins are provi ded for xin clock generation circuit i/o. connect a ceramic oscillator or a crystal oscillator between pins xin and xout. (1) to use an external clock, input it to the xin pin and set xout as the i/o port p9_1. when the pin is not used, treat it as an unassigned pin and use the appropriate handling. xin clock output xout o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between pins xcin and xcout. (1) to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int3 , int5 , int7 iint interrupt input pins. key input interrupt ki0 to ki7 i key input interrupt input pins timer rb trb0o, trb1o o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o timer rc i/o pins timer rh trho o timer rh output pin timer rj trj0io, trj1io i/o timer rj i/o pins serial interface clk0 i/o transfer clock i/o pins rxd0 i serial data input pins txd0 o serial data output pins r01ds0011ej0100 rev.1.00 page 26 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview i: input o: output i/o: input and output note: 1. contact the oscillator manufactur er for oscillation characteristics. table 1.19 pin functions for r8c/la5a group (2) item pin name i/o type description i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin ssu ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin for the a/d converter a/d converter an0 to an6 i a/d converter analog input pins adtrg i ad external trigger input pin comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins ivref1, ivref3 i comparator b reference voltage input pins i/o ports p0_0 to p0_7, p2_0 to p2_7, p3_0 to p3_7, p5_0 to p5_6, p7_0 to p7_2, p8_0 to p8_7, p9_0, p9_1 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. port p8 can be used as led drive ports. segment output seg0 to seg26 o lcd segment output pins common output com0 to com3, comexp o lcd common output pins lcd power supply vl1 i apply the following voltage: 1 v vl1 vcc and vl1 vl2. vl2 i apply the following voltage: vl2 5.5 v and vl1 vl2 vl3. vl3 i apply the following voltage: vl3 5.5 v and vl2 vl3. r01ds0011ej0100 rev.1.00 page 27 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview i: input o: output i/o: input and output note: 1. contact the oscillator manufactur er for oscillation characteristics. table 1.20 pin functions for r8c/LA8A group (1) item pin name i/o type description power supply input vcc, vss ? apply 1. 8 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i driving this pin low resets the mcu. mode mode i connect this pin to vcc via a resistor. power-off 0 mode exit input wkup0 i this pin is provided for input to exit the mode used in power-off 0 mode. connect to vss when not using power-off 0 mode. wkup1 i this pin is provided for input to exit the mode used in power-off 0 mode. xin clock input xin i these pins are provi ded for xin clock generation circuit i/o. connect a ceramic oscillator or a crystal oscillator between pins xin and xout. (1) to use an external clock, input it to the xin pin and set xout as the i/o port p9_1. when the pin is not used, treat it as an unassigned pin and use the appropriate handling. xin clock output xout o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between pins xcin and xcout. (1) to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int7 iint interrupt input pins. key input interrupt ki0 to ki7 i key input interrupt input pins timer rb trb0o, trb1o o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o timer rc i/o pins timer rh trho o timer rh output pin timer rj trj0io, trj1io, trj2io i/o timer rj i/o pins trj0io, trj1io, trj2io o timer rj output pins serial interface clk0, clk2 i/o transfer clock i/o pins rxd0, rxd2 i serial data input pins txd0, txd2 o serial data output pins cts2 i transmission control input pin rts2 o reception control output pin scl2 i/o i 2 c mode clock i/o pin sda2 i/o i 2 c mode data i/o pin r01ds0011ej0100 rev.1.00 page 28 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 1. overview i: input o: output i/o: input and output note: 1. contact the oscillator manufactur er for oscillation characteristics. table 1.21 pin functions for r8c/LA8A group (2) item pin name i/o type description i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin ssu ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin for the a/d converter a/d converter an0 to an11 i a/d converter analog input pins adtrg i ad external trigger input pin comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins ivref1, ivref3 i comparator b reference voltage input pins i/o ports p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_6, p6_0 to p6_7 p7_0 to p7_6, p8_0 to p8_7, p9_0, p9_1 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. ports p7_0, p7_1 and p8 can be used as led drive ports. segment output seg0 to seg39 o lcd segment output pins common output com0 to com3, comexp o lcd common output pins lcd power supply vl1 i apply the following voltage: 1 v vl1 vcc and vl1 vl2. vl2 i apply the following voltage: vl2 5.5 v and vl1 vl2 vl3. vl3 i apply the following voltage: vl3 5.5 v and vl2 vl3. r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 2. central processing unit (cpu) r01ds0011ej0100 rev.1.00 page 29 of 102 dec 21, 2010 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register banks. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high-order bits of intb are intbh and the 16 low-order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers configure a register bank. there are two sets of register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1) r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 2. central processing unit (cpu) r01ds0011ej0100 rev.1.00 page 30 of 102 dec 21, 2010 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starti ng address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operati on results in an overflow; otherwise to 0. r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 2. central processing unit (cpu) r01ds0011ej0100 rev.1.00 page 31 of 102 dec 21, 2010 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined. r8c/la3a group, r8c/la5a group, r8c/ la6a group, r8c/LA8A group 3. memory r01ds0011ej0100 rev.1.00 page 32 of 102 dec 21, 2010 3. memory figure 3.1 is a memory map of each group. each gr oup has a 1-mbyte address space from addresses 00000h to fffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. the starting ad dress of each interrupt routine is stored here. the internal rom (data flash) is allocated addresses 03000h to 037ffh. the internal ram is allocated higher addresses, beginning with address 00400h. for example, a 3.5-kbyte internal ram area is allocated addresses 00400h to 011ffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated addresses 00000h to 002ffh and 02c00h to 02fffh. peripheral function control registers are allocated here. all unalloca ted spaces within the sfrs are reserved and cannot be accessed by users. figure 3.1 memory map fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram 0ffffh 0ffdch zzzzzh internal rom (program rom) undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor address break (reserved) reset 037ffh 03000h internal rom (data flash) (1) 02c00h 02fffh reserved area 0ffd8h part number internal rom internal ram capacity address 0yyyyh capacity address 0xxxxh address zzzzzh data flash available 16 kbytes 0c000h 0ffffh 2 kbytes 00bffh r5f2la34anfp, r5f2la34adfp, r5f2la54anfp, r5f2la54adfp, r5f2la64anfp, r5f2la64anfa, r5f2la64adfp, r5f2la64adfa, r5f2la84anfp, r5f2la84anfa, r5f2la84adfp, r5f2la84adfa sfr (refer to 4. special function registers (sfrs) ) sfr (refer to 4. special function registers (sfrs) ) 8 kbytes 0e000h 0ffffh 2 kbytes 00bffh r5f2la32anfp, r5f2la32adfp, r5f2la52anfp, r5f2la52adfp r5f2la36anfp, r5f2la36adfp, r5f2la56anfp, r5f2la56adfp, r5f2la66anfp, r5f2la66anfa, r5f2la66adfp, r5f2la66adfa, r5f2la86anfp, r5f2la86anfa, r5f2la86adfp, r5f2la86adfa r5f2la67anfp, r5f2la67anfa, r5f2la67adfp, r5f2la67adfa, r5f2la87anfp, r5f2la87anfa, r5f2la87adfp, r5f2la87adfa r5f2la38anfp, r5f2la38adfp, r5f2la58anfp, r5f2la58adfp, r5f2la68anfp, r5f2la68anfa, r5f2la68adfp, r5f2la68adfa, r5f2la88anfp, r5f2la88anfa, r5f2la88adfp, r5f2la88adfa 32 kbytes 08000h 0ffffh 2 kbytes 00bffh 48 kbytes 04000h 0ffffh 3.5 kbytes 011ffh 64 kbytes 04000h 13fffh 3.5 kbytes 011ffh notes: 1. data flash indicates block a (1 kbyte) and block b (1 kbyte). 2. blank spaces are reserved. no access is allowed. r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 33 of 102 dec 21, 2010 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.9 list sfr information for r8c/la5a group, tables 4.10 to 4.18 list sfr informa tion for r8c/LA8A group, and table 4.19 lists the id code areas and option function select area. the description of fered in this chapter is based on the r8c/LA8A group. x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. the cspro bit in the cspr register is set to 1. 3. the cwr bit in the rstfr register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off 0 mode. hardwar e reset, software reset, or watchdog timer reset does not affect this bit. 4. the reset value differs depending on the mode. 5. the csproini bit in the ofs register is set to 0. 6. the lvdas bit in the of s register is set to 1. 7. the lvdas bit in the of s register is set to 0. table 4.1 sfr information for r8c/la5a group (1) (1) address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 00000100b (2) 0006h system clock control register 0 cm0 00100000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register 0 mstcr0 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source dete rmination register rstfr xxh (3) 000ch oscillation stop detection register ocd 00000100b (4) 00h (4) 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h module standby control register 1 mstcr1 00h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (5) 001dh 001eh 001fh 0020h power-off mode control register 0 pomcr0 xxxxxx00b 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator frequency control register 0 frc0 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h 0029h high-speed on-chip oscillator 18 mhz set value register 0 fr18s0 xxh 002ah high-speed on-chip oscillator 18 mhz set value register 1 fr18s1 xxh 002bh 002ch 002dh 002eh 002fh high-speed on-chip oscillator frequenc y control register 1 frc1 when shipping 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (6) 00100000b (7) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circui t control register vw0c 1100x010b (6) 1100x011b (7) 0039h voltage monitor 1 circui t control register vw1c 10001010b r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 34 of 102 dec 21, 2010 x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. selectable by the iicsel bit in the ssuiicsr register. table 4.2 sfr information for r8c/la5a group (2) (1) address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h int7 interrupt control register int7ic xx00x000b 0044h 0045h int5 interrupt control register int5ic xx00x000b 0046h 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h 004ah timer rh interrupt control register trhic xxxxx000b 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register / iic bus interrupt control register (2) ssuic/iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h 0054h 0055h int2 interrupt control register int2ic xx00x000b 0056h timer rj0 interrupt control register trj0ic xxxxx000b 0057h timer rb1 interrupt control register trb1ic xxxxx000b 0058h timer rb0 interrupt control register trb0ic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh timer rj1 interrupt control register trj1ic xxxxx000b 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah lcd interrupt control register lcdic xxxxx000b 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 35 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.3 sfr information for r8c/la5a group (3) (1) address register symbol after reset 0080h timer rj0 control register trj0cr 00h 0081h timer rj0 i/o control register trj0ioc 00h 0082h timer rj0 mode register trj0mr 00h 0083h timer rj0 event pin select register trj0isr 00h 0084h timer rj0 register trj0 ffh 0085h ffh 0086h 0087h 0088h timer rj1 control register trj1cr 00h 0089h timer rj1 i/o control register trj1ioc 00h 008ah timer rj1 mode register trj1mr 00h 008bh timer rj1 event pin select register trj1isr 00h 008ch timer rj1 register trj1 ffh 008dh ffh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h timer rb1 control register trb1cr 00h 0099h timer rb1 one-shot control register trb1ocr 00h 009ah timer rb1 i/o control register trb1ioc 00h 009bh timer rb1 mode register trb1mr 00h 009ch timer rb1 prescaler register trb1pre ffh 009dh timer rb1 secondary register trb1sc ffh 009eh timer rb1 primary register trb1pr ffh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 36 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.4 sfr information for r8c/la5a group (4) (1) address register symbol after reset 00c0h a/d register 0 ad0 xxh 00c1h 000000xxb 00c2h a/d register 1 ad1 xxh 00c3h 000000xxb 00c4h a/d register 2 ad2 xxh 00c5h 000000xxb 00c6h a/d register 3 ad3 xxh 00c7h 000000xxb 00c8h a/d register 4 ad4 xxh 00c9h 000000xxb 00cah a/d register 5 ad5 xxh 00cbh 000000xxb 00cch a/d register 6 ad6 xxh 00cdh 000000xxb 00ceh a/d register 7 ad7 xxh 00cfh 000000xxb 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh a/d control register 2 adcon2 00h 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h 00e2h port p0 direction register pd0 00h 00e3h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h 00e9h port p5 register p5 xxh 00eah 00ebh port p5 direction register pd5 00h 00ech 00edh port p7 register p7 xxh 00eeh 00efh port p7 direction register pd7 00h 00f0h port p8 register p8 xxh 00f1h port p9 register p9 xxh 00f2h port p8 direction register pd8 00h 00f3h port p9 direction register pd9 00h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 37 of 102 dec 21, 2010 x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. this is the reset value after reset by rtcrst bit in trhcr register. table 4.5 sfr information for r8c/la5a group (5) (1) address register symbol after reset 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h timer rb0 control register trb0cr 00h 0109h timer rb0 one-shot control register trb0ocr 00h 010ah timer rb0 i/o control register trb0ioc 00h 010bh timer rb0 mode register trb0mr 00h 010ch timer rb0 prescaler register trb0pre ffh 010dh timer rb0 secondary register trb0sc ffh 010eh timer rb0 primary register trb0pr ffh 010fh 0110h timer rh second data register / counter data register trhsec xxh 00h (2) 0111h timer rh minute data register / compare data register trhmin xxh 00h (2) 0112h timer rh hour data register trhhr 00xxxxxxb 00h (2) 0113h timer rh day-of-the-week data register trhwk 00000xxxb 00h (2) 0114h timer rh date data register trhdy 00xxxxxxb 00000001b (2) 0115h timer rh month data register trhmon 000xxxxxb 00000001b (2) 0116h timer rh year data register trhyr xxh 00h (2) 0117h timer rh control register trhcr xxx00x0xb 000xx1x0b (2) 0118h timer rh count source select register trhcsr x0001000b 0xxxxxxxb (2) 0119h timer rh clock error correction register trhadj xxh 00h (2) 011ah timer rh interrupt flag register trhifr 00000xxxb 000xx000b (2) 011bh timer rh interrupt enable register trhier xxh 00h (2) 011ch timer rh alarm minute register trhamn xxh 00h (2) 011dh timer rh alarm hour register trhahr xxh 00h (2) 011eh timer rh alarm day-of-the-week register trhawk x0000xxxb 00h (2) 011fh timer rh protect register trhprc 00h x0000000b (2) 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 38 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.6 sfr information for r8c/la5a group (6) (1) address register symbol after reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 39 of 102 dec 21, 2010 x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. selectable by the iicsel bit in the ssuiicsr register. 3. this is the reset value after reset by rtcrst bit in trhcr register. table 4.7 sfr information for r8c/la5a group (7) (1) address register symbol after reset 0180h timer rj pin select register trjsr 00h 0181h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h 0185h 0186h 0187h 0188h uart0 pin select register u0sr 00h 0189h 018ah 018bh 018ch ssu/iic pin select register ssuiicsr 00h 018dh timer rh second interrupt control register trhicr x0xxxxxxb 00000001b (3) 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h ss bit counter register ssbr 1 1111000b 0194h ss transmit data register l / iic bus transmit data register (2) sstdr/icdrt ffh 0195h ss transmit data register h (2) sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr/icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh/iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl/iccr2 01111101b 019ah ss mode register / iic bus mode register (2) ssmr/icmr 00010000b/00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser/icier 00h 019ch ss status register / iic bus status register (2) sssr/icsr 00h/0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2/sar 00h 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 000000x0b 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 40 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.8 sfr information for r8c/la5a group (8) (1) address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh 01c1h xxh 01c2h 0000xxxxb 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh 01c5h xxh 01c6h 0000xxxxb 01c7h address match interrupt enable register 1 aier1 00h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h port p0 pull-up control register p0pur 00h 01e1h 01e2h port p2 pull-up control register p2pur 00h 01e3h port p3 pull-up control register p3pur 00h 01e4h 01e5h port p5 pull-up control register p5pur 00h 01e6h 01e7h port p7 pull-up control register p7pur 00h 01e8h port p8 pull-up control register p8pur 00h 01e9h port p9 pull-up control register p9pur 00h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h 01f1h port p8 drive capacity control register p8drr 00h 01f2h 01f3h 01f4h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h input threshold control register 2 vlt2 00h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh external input enable register 1 inten1 00h 01fch int input filter select register 0 intf 00h 01fdh int input filter select register 1 intf1 00h 01feh key input enable register 0 kien 00h 01ffh key input enable register 1 kien1 00h r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 41 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.9 sfr information for r8c/la5a group (9) (1) address register symbol after reset 0200h lcd control register lcr0 00h 0201h 0202h lcd option clock control register lcr2 00h 0203h lcd clock control register lcr3 00h 0204h lcd display control register lcr4 00h 0205h 0206h lcd port select register 0 lse0 00h 0207h lcd port select register 1 lse1 00h 0208h lcd port select register 2 lse2 00h 0209h 020ah 020bh lcd port select register 5 lse5 00h 020ch 020dh 020eh 020fh 0210h lcd display data register lra0l xxh 0211h lra1l xxh 0212h lra2l xxh 0213h lra3l xxh 0214h lra4l xxh 0215h lra5l xxh 0216h lra6l xxh 0217h lra7l xxh 0218h lra8l xxh 0219h lra9l xxh 021ah lra10l xxh 021bh lra11l xxh 021ch lra12l xxh 021dh lra13l xxh 021eh lra14l xxh 021fh lra15l xxh 0220h lra16l xxh 0221h lra17l xxh 0222h lra18l xxh 0223h lra19l xxh 0224h lra20l xxh 0225h lra21l xxh 0226h lra22l xxh 0227h lra23l xxh 0228h lra24l xxh 0229h lra25l xxh 022ah lra26l xxh 022bh 022ch 022dh 022eh 022fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h : 2fffh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 42 of 102 dec 21, 2010 x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. the cspro bit in the cspr register is set to 1. 3. the cwr bit in the rstfr register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off 0 mode. hardwar e reset, software reset, or watchdog timer reset does not affect this bit. 4. the reset value differs depending on the mode. 5. the csproini bit in the ofs register is set to 0. 6. the lvdas bit in the of s register is set to 1. 7. the lvdas bit in the of s register is set to 0. table 4.10 sfr information for r8c/LA8A group (1) (1) address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 00000100b (2) 0006h system clock control register 0 cm0 00100000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register 0 mstcr0 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source dete rmination register rstfr xxh (3) 000ch oscillation stop detection register ocd 00000100b (4) 00h (4) 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h module standby control register 1 mstcr1 00h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (5) 001dh 001eh 001fh 0020h power-off mode control register 0 pomcr0 xxxxxx00b 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator frequency control register 0 frc0 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h 0029h high-speed on-chip oscillator 18 mhz set value register 0 fr18s0 xxh 002ah high-speed on-chip oscillator 18 mhz set value register 1 fr18s1 xxh 002bh 002ch 002dh 002eh 002fh high-speed on-chip oscillator frequenc y control register 1 frc1 when shipping 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (6) 00100000b (7) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circui t control register vw0c 1100x010b (6) 1100x011b (7) 0039h voltage monitor 1 circui t control register vw1c 10001010b r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 43 of 102 dec 21, 2010 x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. selectable by the iicsel bit in the ssuiicsr register. table 4.11 sfr information for r8c/LA8A group (2) (1) address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h int7 interrupt control register int7ic xx00x000b 0044h int6 interrupt control register int6ic xx00x000b 0045h int5 interrupt control register int5ic xx00x000b 0046h int4 interrupt control register int4ic xx00x000b 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h 004ah timer rh interrupt control register trhic xxxxx000b 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register / iic bus interrupt control register (2) ssuic/iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h 0054h 0055h int2 interrupt control register int2ic xx00x000b 0056h timer rj0 interrupt control register trj0ic xxxxx000b 0057h timer rb1 interrupt control register trb1ic xxxxx000b 0058h timer rb0 interrupt control register trb0ic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh timer rj1 interrupt control register trj1ic xxxxx000b 005ch timer rj2 interrupt control register trj2ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh uart2 bus collision detection interrupt control register u2bcnic xxxxx000b 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah lcd interrupt control register lcdic xxxxx000b 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 44 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.12 sfr information for r8c/LA8A group (3) (1) address register symbol after reset 0080h timer rj0 control register trj0cr 00h 0081h timer rj0 i/o control register trj0ioc 00h 0082h timer rj0 mode register trj0mr 00h 0083h timer rj0 event pin select register trj0isr 00h 0084h timer rj0 register trj0 ffh ffh 0085h 0086h 0087h 0088h timer rj1 control register trj1cr 00h 0089h timer rj1 i/o control register trj1ioc 00h 008ah timer rj1 mode register trj1mr 00h 008bh timer rj1 event pin select register trj1isr 00h 008ch timer rj1 register trj1 ffh ffh 008dh 008eh 008fh 0090h timer rj2 control register trj2cr 00h 0091h timer rj2 i/o control register trj2ioc 00h 0092h timer rj2 mode register trj2mr 00h 0093h timer rj2 event pin select register trj2isr 00h 0094h timer rj2 register trj2 ffh ffh 0095h 0096h 0097h 0098h timer rb1 control register trb1cr 00h 0099h timer rb1 one-shot control register trb1ocr 00h 009ah timer rb1 i/o control register trb1ioc 00h 009bh timer rb1 mode register trb1mr 00h 009ch timer rb1 prescaler register trb1pre ffh 009dh timer rb1 secondary register trb1sc ffh 009eh timer rb1 primary register trb1pr ffh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart2 transmit/receive mode register u2mr 00h 00a9h uart2 bit rate register u2brg xxh 00aah uart2 transmit buffer register u2tb xxh 00abh xxh 00ach uart2 transmit/receive control register 0 u2c0 00001000b 00adh uart2 transmit/receive control register 1 u2c1 00000010b 00aeh uart2 receive buffer register u2rb xxh 00afh xxh 00b0h uart2 digital filter function select register urxdf 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh uart2 special mode register 5 u2smr5 00h 00bch uart2 special mode register 4 u2smr4 00h 00bdh uart2 special mode register 3 u2smr3 000x0x0xb 00beh uart2 special mode register 2 u2smr2 x0000000b 00bfh uart2 special mode register u2smr x0000000b r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 45 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.13 sfr information for r8c/LA8A group (4) (1) address register symbol after reset 00c0h a/d register 0 ad0 xxh 00c1h 000000xxb 00c2h a/d register 1 ad1 xxh 00c3h 000000xxb 00c4h a/d register 2 ad2 xxh 00c5h 000000xxb 00c6h a/d register 3 ad3 xxh 00c7h 000000xxb 00c8h a/d register 4 ad4 xxh 00c9h 000000xxb 00cah a/d register 5 ad5 xxh 00cbh 000000xxb 00cch a/d register 6 ad6 xxh 00cdh 000000xxb 00ceh a/d register 7 ad7 xxh 00cfh 000000xxb 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh a/d control register 2 adcon2 00h 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h port p5 register p5 xxh 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech port p6 register p6 xxh 00edh port p7 register p7 xxh 00eeh port p6 direction register pd6 00h 00efh port p7 direction register pd7 00h 00f0h port p8 register p8 xxh 00f1h port p9 register p9 xxh 00f2h port p8 direction register pd8 00h 00f3h port p9 direction register pd9 00h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 46 of 102 dec 21, 2010 x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. this is the reset value after reset by rtcrst bit in trhcr register. table 4.14 sfr information for r8c/LA8A group (5) (1) address register symbol after reset 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h timer rb0 control register trb0cr 00h 0109h timer rb0 one-shot control register trb0ocr 00h 010ah timer rb0 i/o control register trb0ioc 00h 010bh timer rb0 mode register trb0mr 00h 010ch timer rb0 prescaler register trb0pre ffh 010dh timer rb0 secondary register trb0sc ffh 010eh timer rb0 primary register trb0pr ffh 010fh 0110h timer rh second data register / counter data register trhsec xxh 00h (2) 0111h timer rh minute data register / compare data register trhmin xxh 00h (2) 0112h timer rh hour data register trhhr 00xxxxxxb 00h (2) 0113h timer rh day-of-the-week data register trhwk 00000xxxb 00h (2) 0114h timer rh date data register trhdy 00xxxxxxb 00000001b (2) 0115h timer rh month data register trhmon 000xxxxxb 00000001b (2) 0116h timer rh year data register trhyr xxh 00h (2) 0117h timer rh control register trhcr xxx00x0xb 000xx1x0b (2) 0118h timer rh count source select register trhcsr x0001000b 0xxxxxxxb (2) 0119h timer rh clock error correction register trhadj xxh 00h (2) 011ah timer rh interrupt flag register trhifr 00000xxxb 000xx000b (2) 011bh timer rh interrupt enable register trhier xxh 00h (2) 011ch timer rh alarm minute register trhamn xxh 00h (2) 011dh timer rh alarm hour register trhahr xxh 00h (2) 011eh timer rh alarm day-of-the-week register trhawk x0000xxxb 00h (2) 011fh timer rh protect register trhprc 00h x0000000b (2) 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 47 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.15 sfr information for r8c/LA8A group (6) (1) address register symbol after reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 48 of 102 dec 21, 2010 x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. selectable by the iicsel bit in the ssuiicsr register. 3. this is the reset value after reset by rtcrst bit in trhcr register. table 4.16 sfr information for r8c/LA8A group (7) (1) address register symbol after reset 0180h timer rj pin select register trjsr 00h 0181h timer rb pin select register trbsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h 0185h 0186h 0187h 0188h uart0 pin select register u0sr 00h 0189h 018ah uart2 pin select register 0 u2sr0 00h 018bh uart2 pin select register 1 u2sr1 00h 018ch ssu/iic pin select register ssuiicsr 00h 018dh timer rh second interrupt control register trhicr x0xxxxxxb 00000001b (3) 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h ss bit counter register ssbr 1 1111000b 0194h ss transmit data register l / iic bus transmit data register (2) sstdr/icdrt ffh 0195h ss transmit data register h (2) sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr/icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh/iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl/iccr2 01111101b 019ah ss mode register / iic bus mode register (2) ssmr/icmr 00010000b/00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser/icier 00h 019ch ss status register / iic bus status register (2) sssr/icsr 00h/0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2/sar 00h 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 000000x0b 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 49 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.17 sfr information for r8c/LA8A group (8) (1) address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh 01c1h xxh 01c2h 0000xxxxb 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh 01c5h xxh 01c6h 0000xxxxb 01c7h address match interrupt enable register 1 aier1 00h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h port p0 pull-up control register p0pur 00h 01e1h port p1 pull-up control register p1pur 00h 01e2h port p2 pull-up control register p2pur 00h 01e3h port p3 pull-up control register p3pur 00h 01e4h port p4 pull-up control register p4pur 00h 01e5h port p5 pull-up control register p5pur 00h 01e6h port p6 pull-up control register p6pur 00h 01e7h port p7 pull-up control register p7pur 00h 01e8h port p8 pull-up control register p8pur 00h 01e9h port p9 pull-up control register p9pur 00h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h port p7 drive capacity control register p7drr 00h 01f1h port p8 drive capacity control register p8drr 00h 01f2h 01f3h 01f4h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h input threshold control register 2 vlt2 00h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh external input enable register 1 inten1 00h 01fch int input filter select register 0 intf 00h 01fdh int input filter select register 1 intf1 00h 01feh key input enable register 0 kien 00h 01ffh key input enable register 1 kien1 00h r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 50 of 102 dec 21, 2010 x: undefined note: 1. blank spaces are reserved. no access is allowed. table 4.18 sfr information for r8c/LA8A group (9) (1) address register symbol after reset 0200h lcd control register lcr0 00h 0201h 0202h lcd option clock control register lcr2 00h 0203h lcd clock control register lcr3 00h 0204h lcd display control register lcr4 00h 0205h 0206h lcd port select register 0 lse0 00h 0207h lcd port select register 1 lse1 00h 0208h lcd port select register 2 lse2 00h 0209h lcd port select register 3 lse3 00h 020ah lcd port select register 4 lse4 00h 020bh lcd port select register 5 lse5 00h 020ch 020dh 020eh 020fh 0210h lcd display data register lra0l xxh 0211h lra1l xxh 0212h lra2l xxh 0213h lra3l xxh 0214h lra4l xxh 0215h lra5l xxh 0216h lra6l xxh 0217h lra7l xxh 0218h lra8l xxh 0219h lra9l xxh 021ah lra10l xxh 021bh lra11l xxh 021ch lra12l xxh 021dh lra13l xxh 021eh lra14l xxh 021fh lra15l xxh 0220h lra16l xxh 0221h lra17l xxh 0222h lra18l xxh 0223h lra19l xxh 0224h lra20l xxh 0225h lra21l xxh 0226h lra22l xxh 0227h lra23l xxh 0228h lra24l xxh 0229h lra25l xxh 022ah lra26l xxh 022bh lra27l xxh 022ch lra28l xxh 022dh lra29l xxh 022eh lra30l xxh 022fh lra31l xxh 0230h lra32l xxh 0231h lra33l xxh 0232h lra34l xxh 0233h lra35l xxh 0234h lra36l xxh 0235h lra37l xxh 0236h lra38l xxh 0237h lra39l xxh : 2fffh r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group 4 . special function registers (sfrs) r01ds0011ej0100 rev.1.00 page 51 of 102 dec 21, 2010 notes: 1. the option function select area is allocated in the flash memo ry, not in the sfrs. set appropriate values as rom data by a pr ogram. do not write additions to the option function select area. if the block including the option function select area is erased, th e option function select area is set to ffh. when blank products are shipped, the option function select area is set to ffh. it is set to the written value after written by the user. when factory-programming products are shipped, the value of the op tion function select area is the value programmed by the user . 2. the id code areas are allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not write additions to the id code areas. if the block including the id code areas is erased, the id code areas are set to f fh. when blank products are shipped, the id c ode areas are set to ffh. they are set to t he written value after written by the user. when factory-programming products are shipped, the value of the id code areas is the value programmed by the user. table 4.19 id code areas and option function select area address area name symbol after reset : ffdbh option function select register 2 ofs2 (note 1) : ffdfh id1 (note 2) : ffe3h id2 (note 2) : ffebh id3 (note 2) : ffefh id4 (note 2) : fff3h id5 (note 2) : fff7h id6 (note 2) : fffbh id7 (note 2) : ffffh option function select register ofs (note 1) r01ds0011ej0100 rev.1.00 page 52 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5. electrical characteristics 5.1 electrical characte ristics (r8c/la3a group and r8c/la5a group) 5.1.1 absolute maximum ratings notes: 1. for the register settings for each operation, refer to 7. i/o ports and 9. clock generation circuit in the user?s manual: hardware. 2. the vl1 voltage should be vcc or below. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage xin xin-xout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.9 v xin xin-xout oscillation on (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v p5_4/vl1 ? 0.3 to vl2 (2) v p5_5/vl2 vl1 to vl3 v p5_6/vl3 vl2 to 6.5 v other pins ? 0.3 to v cc + 0.3 v v o output voltage xout xin-xout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.9 v xout xin-xout oscillation on (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v com0 to com3 ? 0.3 to vl3 v seg0 to seg26 ? 0.3 to vl3 v other pins ? 0.3 to v cc + 0.3 v p d power dissipation ? 40 c t opr 85 c 500 mw t opr operating ambient temperature ? 20 to 85 (n version)/ ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c r01ds0011ej0100 rev.1.00 page 53 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.1.2 recommended operating conditions notes: 1. the average output current indicates the av erage value of current measured during 100 ms. 2. this applies when the drive capacity of the output transistor is set to high by p8drr register. when the drive capacity is se t to low, the value of any other pin applies. 3. foco20m can be used as the count source for timer rc in the range of v cc = 2.7 v to 5.5v. table 5.2 recommended operating conditions (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 1.8 ? 5.5 v v ss /av ss supply voltage ?0?v v ih input ?h? voltage other than cmos input 4.0 v v cc 5.5 v 0.8 v cc ?v cc v 2.7 v v cc < 4.0 v 0.8 v cc ?v cc v 1.8 v v cc < 2.7 v 0.9 v cc ?v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0.5 v cc ?v cc v 2.7 v v cc < 4.0 v 0.55 v cc ?v cc v 1.8 v v cc < 2.7 v 0.65 v cc ?v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0.65 v cc ?v cc v 2.7 v v cc < 4.0 v 0.7 v cc ?v cc v 1.8 v v cc < 2.7 v 0.8 v cc ?v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0.85 v cc ?v cc v 2.7 v v cc < 4.0 v 0.85 v cc ?v cc v 1.8 v v cc < 2.7 v 0.85 v cc ?v cc v v il input ?l? voltage other than cmos input 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.05 v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0 ? 0.4 v cc v 2.7 v v cc < 4.0 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0 ? 0.55 v cc v 2.7 v v cc < 4.0 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? ? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? ? 80 ma i oh(peak) peak output ?h? current port p8 (2) ?? ? 40 ma other pins ? ? ? 10 ma i oh(avg) average output ?h? current (1) port p8 (2) ?? ? 20 ma other pins ? ? ? 5ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ? ? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ??80ma i ol(peak) peak output ?l? current port p8 (2) ??40ma other pins ? ? 10 ma i ol(avg) average output ?l? current (1) port p8 (2) ??20ma other pins ? ? 5 ma f (xin) xin clock input oscillation frequency 2.7 v v cc 5.5 v 2 ? 20 mhz 1.8 v v cc < 2.7 v 2 ? 8 mhz f (xcin) xcin oscillation frequency 1.8 v v cc 5.5 v ? 32.768 ? khz xcin external clock input frequency 1.8 v v cc 5.5 v ? ? 50 khz foco20m when used as the count source for timer rc (3) 2.7 v v cc 5.5 v 18.432 ? 20 mhz foco-f foco-f frequency 2.7 v v cc 5.5 v - - 20 mhz 1.8 v v cc < 2.7 v - - 8 mhz ? system clock frequency 2.7 v v cc 5.5 v - - 20 mhz 1.8 v v cc < 2.7 v - - 8 mhz f (bclk) cpu clock frequency 2.7 v v cc 5.5 v 0 - 20 mhz 1.8 v v cc < 2.7 v 0 - 8 mhz r01ds0011ej0100 rev.1.00 page 54 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.1 ports p0, p2, p3, p5_0 to p5_6, p 7_0 to p7_2, p8, and p9_0 to p9_1 timing measurement circuit 30 pf p0 p2 p3 p5_0 to p5_6 p7_0 to p7_2 p8 p9_0 to p9_1 r01ds0011ej0100 rev.1.00 page 55 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.1.3 peripheral function characteristics notes: 1. the a/d conversion result will be undefi ned in wait mode, stop mode, power-off mode, when the flash memory stops, and in low-current-consumption mode. do not perfo rm a/d conversion in these states or transition to these states during a/d conversion. 2. this applies when the peripheral functions are stopped. 3. when the analog input voltage is over the reference voltage, th e a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. table 5.3 a/d converter characteristics (v cc /av cc = vref = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ??10bit ? absolute accuracy (2) 10-bit mode v ref = av cc = 5.0 v an0 to an6 input ? ? 3 lsb v ref = av cc = 2.2 v an0 to an6 input ? ? 5 lsb v ref = av cc = 1.8 v an0 to an6 input ? ? 5 lsb 8-bit mode v ref = av cc = 5.0 v an0 to an6 input ? ? 2 lsb v ref = av cc = 2.2 v an0 to an6 input ? ? 2 lsb v ref = av cc = 1.8 v an0 to an6 input ? ? 2 lsb ad a/d conversion clock 4.0 v ref = av cc 5.5 v (1) 1?20mhz 3.2 v ref = av cc 5.5 v (1) 1?16mhz 2.7 v ref = av cc 5.5 v (1) 1?10mhz 1.8 v ref = av cc 5.5 v (1) 1?8mhz ? tolerance level impedance ? 3 ? k ? t conv conversion time 10-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s 8-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? ms t samp sampling time ad = 20 mhz 0.8 ? ? s i vref v ref current vcc = 5 v, xin = f1 = ad = 20 mhz ? 45 ? a v ref reference voltage 1.8 ? av cc v v ia analog input voltage (3) 0?v ref v ocvref on-chip reference voltage 2 mhz ad 4 mhz 1.53 1.70 1.87 v table 5.4 temperature sensor characteristics (v ss = 0 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. v tmp temperature sensor output voltage 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ambient temperature = 25 c 550 600 650 mv ? temperature coefficient 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ambient temperature = 25 c ? ? 2.1 ? mv/ c ? start-up time 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ? ? 200 s i tmp operating current 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ? 100 ? a r01ds0011ej0100 rev.1.00 page 56 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. when the digital filter is disabled. table 5.5 gain amplifier characteristics (v ss = 0 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. v gain gain amplifier operating range 0.4 ? av cc ? 1.0 v ad a/d conversion clock 1 ? 5 mhz table 5.6 comparator b characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. vref ivref1, ivref3 input reference voltage 0 ? v cc ? 1.4 v v i ivcmp1, ivcmp3 input voltage ? 0.3 ? v cc + 0.3 v ? offset ? 5 100 mv t d comparator output delay time (1) v i = vref 100 mv ? ? 1 s i cmp comparator operating current v cc = 5.0 v ? 12 ? a r01ds0011ej0100 rev.1.00 page 57 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 1,000), each bl ock can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple pr ogramming operations, the actual erasure co unt can be reduced by writing to sequential addresses in turn so that as much of the block as possi ble is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, a ttempt to execute the clear status regist er command, then exec ute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.7 flash memory (program rom) characteristics (v cc = 1.8 to 5.5 v and t opr = 0 to 60 c, unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (1) 10,000 (2) ??times ? byte program time ? 80 ? s ? block erase time ? 0.12 ? s t d(sr-sus) time delay from suspend request until suspend ? ? 0.25 + cpu clock 3 cycles ms ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst-ready) time from when command is forcibly terminated until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage 1.8 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (6) ambient temperature = 85 c 10 ? ? year r01ds0011ej0100 rev.1.00 page 58 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple pr ogramming operations, the actual erasure co unt can be reduced by writing to sequential addresses in turn so that as much of the block as possi ble is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, averaging the erasure endurance between blocks a and b can further reduce the actual erasure endurance. it is al so advisable to retain data on the er asure endurance of eac h block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, a ttempt to execute the clear status regist er command, then exec ute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. ? 40 c for d version. 7. the data hold time includes time that the po wer supply is off or the clock is not supplied. figure 5.2 time delay until suspend table 5.8 flash memory (data flash block a and block b) characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (1) 10,000 (2) ??time s ? byte program time (program/erase endurance 10,000 times) ? 150 ? s ? block erase time (program/erase endurance 10,000 times) ?0.05 1 s t d(sr-sus) time delay from suspend request until suspend ? ? 0.25 + cpu clock 3 cycles ms ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst-ready) time from when command is forcibly terminated until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage 1.8 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature ? 20 (6) ?85 c ? data hold time (7) ambient temperature = 85 c 10 ? ? year fst6 bit suspend request (fmr21 bit) fixed time t d(sr-sus) clock-dependent time access restart fst6, fst7: bits in fst register fmr21: bit in fmr2 register fst7 bit r01ds0011ej0100 rev.1.00 page 59 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 2. necessary time until the voltage detection ci rcuit operates when setting to 1 again after setting the vca25 bit in the vca2 r egister to 0. 3. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . notes: 1. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection ci rcuit operates when setting to 1 again after setting the vca26 bit in the vca2 r egister to 0. table 5.9 voltage detection 0 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (1) 1.8 1.90 2.05 v voltage detection level vdet0_1 (1) 2.15 2.35 2.50 v voltage detection level vdet0_2 (1) 2.70 2.85 3.05 v voltage detection level vdet0_3 (1) 3.55 3.80 4.05 v ? voltage detection 0 circuit response time (3) in operation at the falling of vcc from 5 v to (vdet0_0 ? 0.1) v ? 50 500 s in stop mode at the falling of vcc from 5 v to (vdet0_0 ? 0.1) v ? 100 500 s ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 1.5 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ? ? 100 s table 5.10 voltage detection 1 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_0 (1) at the falling of v cc 2.00 2.20 2.40 v voltage detection level vdet1_1 (1) at the falling of v cc 2.15 2.35 2.55 v voltage detection level vdet1_2 (1) at the falling of v cc 2.30 2.50 2.70 v voltage detection level vdet1_3 (1) at the falling of v cc 2.45 2.65 2.85 v voltage detection level vdet1_4 (1) at the falling of v cc 2.60 2.80 3.00 v voltage detection level vdet1_5 (1) at the falling of v cc 2.75 2.95 3.15 v voltage detection level vdet1_6 (1) at the falling of v cc 2.85 3.10 3.40 v voltage detection level vdet1_7 (1) at the falling of v cc 3.00 3.25 3.55 v voltage detection level vdet1_8 (1) at the falling of v cc 3.15 3.40 3.70 v voltage detection level vdet1_9 (1) at the falling of v cc 3.30 3.55 3.85 v voltage detection level vdet1_a (1) at the falling of v cc 3.45 3.70 4.00 v voltage detection level vdet1_b (1) at the falling of v cc 3.60 3.85 4.15 v voltage detection level vdet1_c (1) at the falling of v cc 3.75 4.00 4.30 v voltage detection level vdet1_d (1) at the falling of v cc 3.90 4.15 4.45 v voltage detection level vdet1_e (1) at the falling of v cc 4.05 4.30 4.60 v voltage detection level vdet1_f (1) at the falling of v cc 4.20 4.45 4.75 v ? hysteresis width at the rising of vcc in voltage detection 1 circuit vdet1_0 to vdet1_5 selected ? 0.07 ? v vdet1_6 to vdet1_f selected ? 0.10 ? v ? voltage detection 1 circuit response time (2) in operation at the falling of vcc from 5 v to (vdet1_0 ? 0.1) v ? 60 150 s in stop mode at the falling of vcc from 5 v to (vdet1_0 ? 0.1) v ? 250 500 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s r01ds0011ej0100 rev.1.00 page 60 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. the voltage detection level varies with detection targets. select the level with the vca24 bit in the vca2 register. 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates af ter setting to 1 again after setting the vca27 bit in the vca2 register to 0. note: 1. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 5.3 power-on reset circuit characteristics table 5.11 voltage detection 2 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 (1) at the falling of v cc 3.70 4.0 4.30 v ? hysteresis width at the rising of vcc in voltage detection 2 circuit ?0.10? v ? voltage detection 2 circuit response time (2) in operation at the falling of vcc from 5 v to (vdet2_0 ? 0.1) v ? 20 150 s in stop mode at the falling of vcc from 5 v to (vdet2_0 ? 0.1) v ? 200 500 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.12 power-on reset circuit characteristics (1) (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t rth external power v cc rise gradient 0 ? 50000 mv/msec notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit in the user?s manual: hardware for details. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 reset disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) 1 f oco-s 32 1 f oco-s 32 external power v cc t rth t rth r01ds0011ej0100 rev.1.00 page 61 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. waiting time until the internal power s upply generation circuit stabilizes during power-on. table 5.13 high-speed on-chip osc illator circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency after reset v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 19.2 20 20.8 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 19.0 20 21.0 mhz high-speed on-chip oscillator frequency when the fra4 register correction value is written into the fra1 register and the fra5 register correction value into the fra3 register (1) v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 17.694 18.432 19.169 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 17.510 18.432 19.353 mhz ? oscillation stab ility time ? 5 30 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 530 ? a table 5.14 low-speed on-chip osc illator circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation stab ility time ? ? 35 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a foco-wdt low-speed on-chip oscillator frequency for the watchdog timer 60 125 250 khz ? oscillation stab ility time ? ? 35 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a table 5.15 power supply circuit characteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = 25 c, unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (1) ? ? 2000 s r01ds0011ej0100 rev.1.00 page 62 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. refer to table 5.19 dc characteristics (2), table 5.21 dc characteristics (4), and tabl e 5.23 dc characteristics (6). 2. the vl1 voltage should be vcc or below. table 5.16 lcd drive contro l circuit char acteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. vlcd lcd power supply voltage vlcd = vl3 2.2 ? 5.5 v vl2 vl2 voltage vl1 ? vl3 v vl1 vl1 voltage 1 ? vl2 (2) v f(fr) frame frequency 50 ? 180 hz ilcd lcd drive control circuit current ? (1) ? a table 5.17 power-off mode characteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. ? power-off mode operating supply voltage 1.8 ? 5.5 v r01ds0011ej0100 rev.1.00 page 63 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.1.4 dc characteristics note: 1. this applies when the drive capacity of the output transistor is set to high by p8 drr register. when the drive capacity is se t to low, the value of any other pin applies. table 5.18 dc characteristics (1) [4.0 v vcc 5.5 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p8 (1) v cc = 5v i oh = ? 20 ma v cc ? 2.0 ? v cc v other pins v cc = 5v i oh = ? 5 ma v cc ? 2.0 ? v cc v v ol output ?l? voltage port p8 (1) v cc = 5v i ol = 20 ma ? ? 2.0 v other pins v cc = 5v i ol = 5 ma ? ? 2.0 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int5 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , trcioa, trciob, trcioc, trciod, trj0io, trj1io, trctrg, trcclk, adtrg , rxd0, clk0, ssi, scl, sda, sso 0.05 0.5 ? v reset , wkup0 0.1 0.8 ? v i ih input ?h? current vi = 5 v, v cc = 5 v ? ? 5.0 a i il input ?l? current vi = 0 v, v cc = 5 v ? ? ? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5 v 20 40 80 k ? r fxin feedback resistance xin ?2.0?m ? r fxcin feedback resistance xcin ?14?m ? v ram ram hold voltage during stop mode 1.8 ? ? v r01ds0011ej0100 rev.1.00 page 64 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. vcc = 4.0 v to 5.5 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 5.0 v 4. vlcd = vcc, external division resistors are used for vl3 to vl 1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg26 are selecte d, and segment and common output pins are open. the standard value does not include the current that flows through external division resistors . table 5.19 dc characteristics (2) [4.0 v vcc 5.5 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max . xin (2) xcin high- speed low- speed i cc power supply current (1) high- speed clock mode 20 mhz off off 125 khz no division ? ? 4.7 10 ma 16 mhz off off 125 khz no division ? ? 3.9 8 ma 10 mhz off off 125 khz no division ? ? 2.3 ? ma 20 mhz off off off no division fmr27 = 1 mstcr0 = beh mstcr1 = 3fh flash memory off program operation on ram module standby setting enabled ?3.1?ma 20 mhz off off 125 khz divide-by-8 ? ? 1.8 ? ma 16 mhz off off 125 khz divide-by-8 ? ? 1.5 ? ma 10 mhz off off 125 khz divide-by-8 ? ? 1.0 ? ma high- speed on-chip oscillator mode off off 20 mhz 125 khz no division ? ? 5.0 11 ma off off 20 mhz 125 khz divide-by-8 ? ? 2.1 ? ma off off 4 mhz 125 khz divide-by-16 mstcr0 = beh mstcr1 = 3fh ?0.9?ma low- speed on-chip oscillator mode off off off 125 khz no division fmr27 = 1 vca20 = 0 ? 110 320 a off off off 125 khz divide-by-8 fmr27 = 1 vca20 = 0 ?63220 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?60220 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?46? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?9.050 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?2.833 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer rh operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?4.6? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer rh operation in real- time clock mode ?2.4? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?0.52.2 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ?1.2? a power- off mode off off off off ? ? power-off 0 topr = 25 c ? 0.01 0.1 a off off off off ? ? power-off 0 topr = 85 c ?0.03? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 25 c ?1.86.4 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 85 c ?2.7? a r01ds0011ej0100 rev.1.00 page 65 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. this applies when the drive capacity of the output transistor is set to high by p8 drr register. when the drive capacity is se t to low, the value of any other pin applies. table 5.20 dc characteristics (3) [2.7 v vcc < 4.0 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p8 (1) i oh = ? 5 ma v cc ? 0.5 ? v cc v other pins i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage port p8 (1) i ol = 5 ma ? ? 0.5 v other pins i ol = 1 ma ? ? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int5 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , trcioa, trciob, trcioc, trciod, trj0io, trj1io, trctrg, trcclk, adtrg , rxd0, clk0, ssi, scl, sda, sso 0.05 0.4 ? v reset , wkup0 0.1 0.8?v i ih input ?h? current vi = 3 v, v cc = 3 v ? ? 5.0 a i il input ?l? current vi = 0 v, v cc = 3 v ? ? ? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 3 v 25 80 140 k ? r fxin feedback resistance xin ? 2.0 ? m ? r fxcin feedback resistance xcin ? 14 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r01ds0011ej0100 rev.1.00 page 66 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. vcc = 2.7 v to 4.0 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 3.0 v 4. vlcd = vcc, external division resistors are used for vl3 to vl 1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg26 are selecte d, and segment and common output pins are open. the standard value does not include the current that flows through external division resistors . table 5.21 dc characteristics (4) [2.7 v vcc < 4.0 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max . xin (2) xcin high- speed low- speed i cc power supply current (1) high- speed clock mode 20 mhz off off 125 khz no division ? ? 4.7 10 ma 10 mhz off off 125 khz no division ? ? 2.3 6 ma 20 mhz off off off no division fmr27 = 1 mstcr0 = beh mstcr1 = 3fh flash memory off program operation on ram module standby setting enabled ?2.9?ma 20 mhz off off 125 khz divide-by-8 ? ? 1.8 ? ma 10 mhz off off 125 khz divide-by-8 ? ? 1.0 ? ma high- speed on-chip oscillator mode off off 20 mhz 125 khz no division ? ? 5.0 11 ma off off 20 mhz 125 khz divide-by-8 ? ? 2.1 ? ma off off 10 mhz 125 khz no division ? ? 2.9 ? ma off off 10 mhz 125 khz divide-by-8 ? ? 1.5 ? ma off off 4 mhz 125 khz divide-by-16 mstcr0 = beh mstcr1 = 3fh ?0.9?ma low- speed on-chip oscillator mode off off off 125 khz no division fmr27 = 1 vca20 = 0 ? 106 300 a off off off 125 khz divide-by-8 fmr27 = 1 vca20 = 0 ?54200 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?54200 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?36? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?9.050 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?2.531 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer rh operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?3.1? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer rh operation in real- time clock mode ?1.7? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?0.52.2 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ?1.2? a power- off mode off off off off ? ? power-off 0 topr = 25 c ? 0.01 0.1 a off off off off ? ? power-off 0 topr = 85 c ?0.02? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 25 c ?1.34.5 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 85 c ?2.2? a r01ds0011ej0100 rev.1.00 page 67 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. this applies when the drive capacity of the output transistor is set to high by p8 drr register. when the drive capacity is se t to low, the value of any other pin applies. table 5.22 dc characteristics (5) [1.8 v vcc < 2.7 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p8 (1) i oh = ? 2 ma v cc ? 0.5 ? v cc v other pins i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage port p8 (1) i ol = 2 ma ? ? 0.5 v other pins i ol = 1 ma ? ? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int5 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , trcioa, trciob, trcioc, trciod, trj0io, trj1io, trctrg, trcclk, adtrg , rxd0, clk0, ssi, scl, sda, sso 0.05 0.4 ? v reset , wkup0 0.1 0.8 ? v i ih input ?h? current vi = 1.8 v, v cc = 1.8 v ? ? 4.0 a i il input ?l? current vi = 0 v, v cc = 1.8 v ? ? ? 4.0 a r pullup pull-up resistance vi = 0 v, v cc = 1.8 v 85 220 500 k ? r fxin feedback resistance xin ? 2.0 ? m ? r fxcin feedback resistance xcin ? 14 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r01ds0011ej0100 rev.1.00 page 68 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. vcc = 1.8 v to 2.7 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 2.2 v 4. vlcd = vcc, external division resistors are used for vl3 to vl 1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg26 are selecte d, and segment and common output pins are open.the standard value does not includ e the current that flows through external division resistors. table 5.23 dc characteristics (6) [1.8 v vcc < 2.7 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max . xin (2) xcin high- speed low- speed i cc power supply current (1) high- speed clock mode 8 mhz off off 125 khz no division ? ? 2.1 ? ma 8 mhz off off 125 khz divide-by-8 ? ? 0.9 ? ma high- speed on-chip oscillator mode off off 5 mhz 125 khz no division ? ? 1.8 5 ma off off 5 mhz 125 khz divide-by-8 ? ? 1.1 ? ma off off 4 mhz 125 khz divide-by-16 mstcr0 = beh mstcr1 = 3fh ?0.9?ma low- speed on-chip oscillator mode off off off 125 khz no division fmr27 = 1 vca20 = 0 ? 106 300 a off off off 125 khz divide-by-8 fmr27 = 1 vca20 = 0 ?54200 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?54200 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?36? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?9.050 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?2.531 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer rh operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?2.4? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer rh operation in real- time clock mode ?1.7? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?0.52.2 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ?1.2? a power- off mode off off off off ? ? power-off 0 topr = 25 c ? 0.01 0.1 a off off off off ? ? power-off 0 topr = 85 c ?0.02? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 25 c ?1.24 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 85 c ?2? a r01ds0011ej0100 rev.1.00 page 69 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.1.5 ac characteristics note: 1. 1t cyc = 1/f1(s) table 5.24 timing requirements of synchronous serial communication unit (ssu) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ? - t cyc (1) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ? ? 1 t cyc (1) slave ? ? 1 s t fall ssck clock falling time master ? ? 1 t cyc (1) slave ? ? 1 s t su sso, ssi data input setup time 100 ? ? ns t h sso, ssi data input hold time 1 ? ? t cyc (1) t lead scs setup time slave 1t cyc + 50 ? ? ns t lag scs hold time slave 1t cyc + 50 ? ? ns t od sso, ssi data output delay time ? ? 1t cyc + 20 ns t sa ssi slave access time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns r01ds0011ej0100 rev.1.00 page 70 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.4 i/o timing of synchronous serial communication unit (ssu) (master) v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register r01ds0011ej0100 rev.1.00 page 71 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.5 i/o timing of synchronous serial communication unit (ssu) (slave) v ih or v oh v il or v ol scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register r01ds0011ej0100 rev.1.00 page 72 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.6 i/o timing of synchronous serial communication unit (ssu) (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v il or v ol r01ds0011ej0100 rev.1.00 page 73 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.25 timing requirements of i 2 c bus interface (1) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (1) ??ns t sclh scl input ?h? width 3t cyc + 300 (1) ??ns t scll scl input ?l? width 5t cyc + 500 (1) ??ns t sf scl, sda input fall time ? ? 300 ns t sp scl, sda input spike pulse rejection time ? ? 1t cyc (1) ns t buf sda input bus-free time 5t cyc (1) ??ns t stah start condition input hold time 3t cyc (1) ??ns t stas retransmit start condition input setup time 3t cyc (1) ??ns t stop stop condition input setup time 3t cyc (1) ??ns t sdas data input setup time 1t cyc + 40 (1) ??ns t sdah data input hold time 10 ? ? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition r01ds0011ej0100 rev.1.00 page 74 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.8 external clock input timing diagram figure 5.9 input timing of trjiio table 5.26 external clock input (xin, xcin) (v ss = 0 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(xin) xin input cycle time 200 ? 50 ? 50 ? ns t wh(xin) xin input ?h? width 90 ? 24 ? 24 ? ns t wl(xin) xin input ?l? width 90 ? 24 ? 24 ? ns t c(xcin) xcin input cycle time 20 ? 20 ? 20 ? s t wh(xcin) xcin input ?h? width 10 ? 10 ? 10 ? s t wl(xcin) xcin input ?l? width 10 ? 10 ? 10 ? s table 5.27 timing requirements of trjiio (i = 0 or 1) (v ss = 0 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(trjio) trjiio input cycle time 500 ? 300 ? 100 ? ns t wh(trjio) trjiio input ?h? width 200 ? 120 ? 40 ? ns t wl(trjio) trjiio input ?l? width 200 ? 120 ? 40 ? ns external clock input t wh(xin), t wh(xcin) t c(xin), t c(xcin) t wl(xin), t wl(xcin) trjiio input t c(trjio) t wl(trjio) t wh(trjio) r01ds0011ej0100 rev.1.00 page 75 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.10 input and output timing of serial interface notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.11 input timing of external interrupt int i and key input interrupt kii table 5.28 timing requirements of serial interface (v ss = 0 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(ck) clk0 input cycle time 800 ? 300 ? 200 ? ns t w(ckh) clk0 input ?h? width 400 ? 150 ? 100 ? ns t w(ckl) clk0 input ?l? width 400 ? 150 ? 100 ? ns t d(c-q) txd0 output delay time ? 200 ? 80 ? 50 ns t h(c-q) txd0 hold time 0?0?0?ns t su(d-c) rxd0 input setup time 150 ? 70 ? 50 ? ns t h(c-d) rxd0 input hold time 90 ? 90 ? 90 ? ns table 5.29 timing requirements of external interrupt inti (i = 0 to 3, 5, 7) and key input interrupt kii (i = 0 to 7) (v ss = 0 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t w(inh) inti input ?h? width, kii input ?h? width 1000 (1) ? 380 (1) ? 250 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 1000 (2) ? 380 (2) ? 250 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clk0 txd0 rxd0 inti input (i = 0 to 3, 5, 7) t w(inl) t w(inh) kii input (i = 0 to 7) r01ds0011ej0100 rev.1.00 page 76 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.2 electrical characte ristics (r8c/la6a group and r8c/LA8A group) 5.2.1 absolute maximum ratings notes: 1. for the register settings for each operation, refer to 7. i/o ports and 9. clock generation circuit in the user?s manual: hardware. 2. the vl1 voltage should be vcc or below. table 5.30 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage xin xin-xout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.9 v xin xin-xout oscillation on (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v p5_4/vl1 ? 0.3 to vl2 (2) v p5_5/vl2 vl1 to vl3 v p5_6/vl3 vl2 to 6.5 v other pins ? 0.3 to v cc + 0.3 v v o output voltage xout xin-xout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.9 v xout xin-xout oscillation on (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v com0 to com3 ? 0.3 to vl3 v seg0 to seg39 ? 0.3 to vl3 v other pins ? 0.3 to v cc + 0.3 v p d power dissipation ? 40 c t opr 85 c 500 mw t opr operating ambient temperature ? 20 to 85 (n version)/ ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c r01ds0011ej0100 rev.1.00 page 77 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.2.2 recommended operating conditions notes: 1. the average output current indicates the average value of current measured during 100 ms. 2. this applies when the drive capacity of the output transistor is set to high by registers p7drr and p8drr. when the drive cap acity is set to low, the value of any other pin applies. 3. foco20m can be used as the count source for timer rc in the range of v cc = 2.7 v to 5.5v. table 5.31 recommended operating conditions (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 1.8 ? 5.5 v v ss /av ss supply voltage ?0?v v ih input ?h? voltage other than cmos input 4.0 v v cc 5.5 v 0.8 v cc ?v cc v 2.7 v v cc < 4.0 v 0.8 v cc ?v cc v 1.8 v v cc < 2.7 v 0.9 v cc ?v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0.5 v cc ?v cc v 2.7 v v cc < 4.0 v 0.55 v cc ?v cc v 1.8 v v cc < 2.7 v 0.65 v cc ?v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0.65 v cc ?v cc v 2.7 v v cc < 4.0 v 0.7 v cc ?v cc v 1.8 v v cc < 2.7 v 0.8 v cc ?v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0.85 v cc ?v cc v 2.7 v v cc < 4.0 v 0.85 v cc ?v cc v 1.8 v v cc < 2.7 v 0.85 v cc ?v cc v v il input ?l? voltage other than cmos input 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.05 v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0 ? 0.4 v cc v 2.7 v v cc < 4.0 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0 ? 0.55 v cc v 2.7 v v cc < 4.0 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? ? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? ? 80 ma i oh(peak) peak output ?h? current port p7_0, p7_1, p8 (2) ?? ? 40 ma other pins ? ? ? 10 ma i oh(avg) average output ?h? current (1) port p7_0, p7_1, p8 (2) ?? ? 20 ma other pins ? ? ? 5ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ? ? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ??80ma i ol(peak) peak output ?l? current port p7_0, p7_1, p8 (2) ??40ma other pins ? ? 10 ma i ol(avg) average output ?l? current (1) port p7_0, p7_1, p8 (2) ??20ma other pins ? ? 5 ma f (xin) xin clock input oscillation frequency 2.7 v v cc 5.5 v 2 ? 20 mhz 1.8 v v cc < 2.7 v 2 ? 8 mhz f (xcin) xcin oscillation frequency 1.8 v v cc 5.5 v ? 32.768 ? khz xcin external clock input frequency 1.8 v v cc 5.5 v ? ? 50 khz foco20m when used as the count source for timer rc (3) 2.7 v v cc 5.5 v 18.432 ? 20 mhz foco-f foco-f frequency 2.7 v v cc 5.5 v - - 20 mhz 1.8 v v cc < 2.7 v - - 8 mhz ? system clock frequency 2.7 v v cc 5.5 v - - 20 mhz 1.8 v v cc < 2.7 v - - 8 mhz f (bclk) cpu clock frequency 2.7 v v cc 5.5 v 0 - 20 mhz 1.8 v v cc < 2.7 v 0 - 8 mhz r01ds0011ej0100 rev.1.00 page 78 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.12 ports p0 to p4, p5_0 to p5_6, p6, p7_0 to p7_6, p8, and p9_0 to p9_1 timing measurement circuit 30 pf p0 p1 p2 p3 p4 p5_0 to p5_6 p6 p7_0 to p7_6 p8 p9_0 to p9_1 r01ds0011ej0100 rev.1.00 page 79 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.2.3 peripheral function characteristics notes: 1. the a/d conversion result will be undefi ned in wait mode, stop mode, power-off mode, when the flash memory stops, and in low-current-consumption mode. do not perform a/d conversion in these states or transition to these states during a/d conversion. 2. this applies when the peripheral functions are stopped. 3. when the analog input voltage is over the reference voltage, th e a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. table 5.32 a/d converter characteristics (v cc /av cc = vref = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ??10bit ? absolute accuracy (2) 10-bit mode v ref = av cc = 5.0 v an0 to an11 input ? ? 3 lsb v ref = av cc = 2.2 v an0 to an11 input ? ? 5 lsb v ref = av cc = 1.8 v an0 to an11 input ? ? 5 lsb 8-bit mode v ref = av cc = 5.0 v an0 to an11 input ? ? 2 lsb v ref = av cc = 2.2 v an0 to an11 input ? ? 2 lsb v ref = av cc = 1.8 v an0 to an11 input ? ? 2 lsb ad a/d conversion clock 4.0 v ref = av cc 5.5 v (1) 1?20mhz 3.2 v ref = av cc 5.5 v (1) 1?16mhz 2.7 v ref = av cc 5.5 v (1) 1?10mhz 1.8 v ref = av cc 5.5 v (1) 1?8mhz ? tolerance level impedance ? 3 ? k ? t conv conversion time 10-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s 8-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? ms t samp sampling time ad = 20 mhz 0.8 ? ? s i vref v ref current vcc = 5 v, xin = f1 = ad = 20 mhz - 45 ? a v ref reference voltage 1.8 ? av cc v v ia analog input voltage (3) 0?v ref v ocvref on-chip reference voltage 2 mhz ad 4 mhz 1.53 1.70 1.87 v table 5.33 temperature sensor characteristics (vss = 0 v and topr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. v tmp temperature sensor output voltage 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ambient temperature = 25 c 550 600 650 mv ? temperature coefficient 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ambient temperature = 25 c ? ? 2.1 ? mv/ c ? start-up time 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ? ? 200 s i tmp operating current 1.8 v vref = av cc 5.5 v ad = 1.0 mhz to 5.0 mhz ? 100 ? a r01ds0011ej0100 rev.1.00 page 80 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. when the digital filter is disabled. notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 1,000), each bl ock can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possi ble is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, a ttempt to execute the clear status regist er command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.34 gain amplifier characteristics (vss = 0 v and topr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. vgain gain amplifier operating range 0.4 ? avcc ? 1.0 v ad a/d conversion clock 1 ? 5 mhz table 5.35 comparator b characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. vref ivref1, ivref3 input reference voltage 0 ? v cc ? 1.4 v v i ivcmp1, ivcmp3 input voltage -0.3 ? v cc + 0.3 v ? offset ? 5 100 mv t d comparator output delay time (1) v i = vref 100 mv ? ? 1 s i cmp comparator operating current v cc = 5.0 v ? 12 ? a table 5.36 flash memory (program rom) characteristics (v cc = 1.8 to 5.5 v and t opr = 0 to 60 c, unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (1) 10,000 (2) ??times ? byte program time ? 80 ? s ? block erase time ? 0.12 ? s t d(sr-sus) time delay from suspend request until suspend ? ? 0.25 + cpu clock 3 cycles ms ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst-ready) time from when command is forcibly terminated until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage 1.8 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (6) ambient temperature = 85 c 10 ? ? year r01ds0011ej0100 rev.1.00 page 81 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possi ble is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, averaging the erasure endurance between blocks a and b can further reduce the actual erasure endurance. it is al so advisable to retain data on the er asure endurance of eac h block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, a ttempt to execute the clear status regist er command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. ? 40 c for d version. 7. the data hold time includes time that the po wer supply is off or the clock is not supplied. figure 5.13 time delay until suspend table 5.37 flash memory (data flash block a and block b) characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (1) 10,000 (2) ??time s ? byte program time (program/erase endurance 10,000 times) ? 150 ? s ? block erase time (program/erase endurance 10,000 times) ?0.05 1 s t d(sr-sus) time delay from suspend request until suspend ? ? 0.25 + cpu clock 3 cycles ms ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst-ready) time from when command is forcibly terminated until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage 1.8 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature ? 20 (6) ?85 c ? data hold time (7) ambient temperature = 85 c 10 ? ? year fst6 bit suspend request (fmr21 bit) fixed time t d(sr-sus) clock-dependent time access restart fst6, fst7: bits in fst register fmr21: bit in fmr2 register fst7 bit r01ds0011ej0100 rev.1.00 page 82 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 2. necessary time until the voltage detection ci rcuit operates when setting to 1 again after setting the vca25 bit in the vca2 r egister to 0. 3. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . notes: 1. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection ci rcuit operates when setting to 1 again after setting the vca26 bit in the vca2 r egister to 0. table 5.38 voltage detection 0 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (1) 1.8 1.90 2.05 v voltage detection level vdet0_1 (1) 2.15 2.35 2.50 v voltage detection level vdet0_2 (1) 2.70 2.85 3.05 v voltage detection level vdet0_3 (1) 3.55 3.80 4.05 v ? voltage detection 0 circuit response time (3) in operation at the falling of vcc from 5 v to (vdet0_0 ? 0.1) v ? 50 500 s in stop mode at the falling of vcc from 5 v to (vdet0_0 ? 0.1) v ? 100 500 s ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 1.5 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ? ? 100 s table 5.39 voltage detection 1 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_0 (1) at the falling of v cc 2.00 2.20 2.40 v voltage detection level vdet1_1 (1) at the falling of v cc 2.15 2.35 2.55 v voltage detection level vdet1_2 (1) at the falling of v cc 2.30 2.50 2.70 v voltage detection level vdet1_3 (1) at the falling of v cc 2.45 2.65 2.85 v voltage detection level vdet1_4 (1) at the falling of v cc 2.60 2.80 3.00 v voltage detection level vdet1_5 (1) at the falling of v cc 2.75 2.95 3.15 v voltage detection level vdet1_6 (1) at the falling of v cc 2.85 3.10 3.40 v voltage detection level vdet1_7 (1) at the falling of v cc 3.00 3.25 3.55 v voltage detection level vdet1_8 (1) at the falling of v cc 3.15 3.40 3.70 v voltage detection level vdet1_9 (1) at the falling of v cc 3.30 3.55 3.85 v voltage detection level vdet1_a (1) at the falling of v cc 3.45 3.70 4.00 v voltage detection level vdet1_b (1) at the falling of v cc 3.60 3.85 4.15 v voltage detection level vdet1_c (1) at the falling of v cc 3.75 4.00 4.30 v voltage detection level vdet1_d (1) at the falling of v cc 3.90 4.15 4.45 v voltage detection level vdet1_e (1) at the falling of v cc 4.05 4.30 4.60 v voltage detection level vdet1_f (1) at the falling of v cc 4.20 4.45 4.75 v ? hysteresis width at the rising of vcc in voltage detection 1 circuit vdet1_0 to vdet1_5 selected ? 0.07 ? v vdet1_6 to vdet1_f selected ? 0.10 ? v ? voltage detection 1 circuit response time (2) in operation at the falling of vcc from 5 v to (vdet1_0 ? 0.1) v ? 60 150 s in stop mode at the falling of vcc from 5 v to (vdet1_0 ? 0.1) v ? 250 500 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s r01ds0011ej0100 rev.1.00 page 83 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. the voltage detection level varies with detection targets. se lect the level with the vca24 bit in the vca2 register. 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detecti on circuit operates after setting to 1 again after setting the vca27 bit in the vca2 register to 0. note: 1. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 5.14 power-on reset circuit characteristics table 5.40 voltage detection 2 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 (1) at the falling of v cc 3.70 4.0 4.30 v ? hysteresis width at the rising of vcc in voltage detection 2 circuit ?0.10? v ? voltage detection 2 circuit response time (2) in operation at the falling of vcc from 5 v to (vdet2_0 ? 0.1) v ? 20 150 s in stop mode at the falling of vcc from 5 v to (vdet2_0 ? 0.1) v ? 200 500 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.41 power-on reset circuit characteristics (1) (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t rth external power v cc rise gradient 0 ? 50000 mv/msec notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit in the user?s manual: hardware for details. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 reset disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) 1 f oco-s 32 1 f oco-s 32 external power v cc t rth t rth r01ds0011ej0100 rev.1.00 page 84 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. waiting time until the internal power s upply generation circuit stabilizes during power-on. table 5.42 high-speed on-chip osc illator circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency after reset v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 19.2 20 20.8 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 19.0 20 21.0 mhz high-speed on-chip oscillator frequency when the fra4 register correction value is written into the fra1 register and the fra5 register correction value into the fra3 register (1) v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 17.694 18.432 19.169 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 17.510 18.432 19.353 mhz ? oscillation stability time ? 5 30 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 530 ? a table 5.43 low-speed on-chip osc illator circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation stability time ? ? 35 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a foco-wdt low-speed on-chip oscillator frequency for the watchdog timer 60 125 250 khz ? oscillation stability time ? ? 35 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a table 5.44 power supply circuit characteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = 25 c, unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (1) ? ? 2000 s r01ds0011ej0100 rev.1.00 page 85 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. refer to table 5.48 dc characteristics (2), table 5.50 dc characteristics (4), and tabl e 5.52 dc characteristics (6). 2. the vl1 voltage should be vcc or below. table 5.45 lcd drive contro l circuit char acteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. vlcd lcd power supply voltage vlcd = vl3 2.2 ? 5.5 v vl2 vl2 voltage vl1 ? vl3 v vl1 vl1 voltage 1 ? vl2 (2) v f(fr) frame frequency 50 ? 180 hz ilcd lcd drive control circuit current ? (1) ? a table 5.46 power-off mode characteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. ? power-off mode operating supply voltage 1.8 ? 5.5 v r01ds0011ej0100 rev.1.00 page 86 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.2.4 dc characteristics note: 1. this applies when the drive capacity of the output transistor is set to high by registers p7drr and p8drr. when the drive capacity is set to low, the value of any other pin applies. table 5.47 dc characteristics (1) [4.0 v vcc 5.5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p7_0, p7_1, p8 (1) v cc = 5v i oh = ? 20 ma v cc ? 2.0 ? v cc v other pins v cc = 5v i oh = ? 5 ma v cc ? 2.0 ? v cc v v ol output ?l? voltage port p7_0, p7_1, p8 (1) v cc = 5v i ol = 20 ma ? ? 2.0 v other pins v cc = 5v i ol = 5 ma ? ? 2.0 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , trcioa, trciob, trcioc, trciod, trj0io, trj1io, trj2io, trctrg, trcclk, adtrg , rxd0, rxd2, clk0, clk2, ssi, scl, sda, sso 0.05 0.5 ? v reset , wkup0 0.1 0.8 ? v i ih input ?h? current vi = 5 v, v cc = 5 v ? ? 5.0 a i il input ?l? current vi = 0 v, v cc = 5 v ? ? ? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5 v 20 40 80 k ? r fxin feedback resistance xin ?2.0?m ? r fxcin feedback resistance xcin ?14?m ? v ram ram hold voltage during stop mode 1.8 ? ? v r01ds0011ej0100 rev.1.00 page 87 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. vcc = 4.0 v to 5.5 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 5.0 v 4. vlcd = vcc, external division resistors are used for vl3 to vl 1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg39 are selecte d, and segment and common output pins are open. the standard value does not include the current that flows through external division resistors . table 5.48 dc characteristics (2) [4.0 v vcc 5.5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max . xin (2) xcin high- speed low- speed i cc power supply current (1) high- speed clock mode 20 mhz off off 125 khz no division ? ? 4.7 10 ma 16 mhz off off 125 khz no division ? ? 3.9 8 ma 10 mhz off off 125 khz no division ? ? 2.3 ? ma 20 mhz off off off no division fmr27 = 1 mstcr0 = beh mstcr1 = 3fh flash memory off program operation on ram module standby setting enabled ?3.1?ma 20 mhz off off 125 khz divide-by-8 ? ? 1.8 ? ma 16 mhz off off 125 khz divide-by-8 ? ? 1.5 ? ma 10 mhz off off 125 khz divide-by-8 ? ? 1.0 ? ma high- speed on-chip oscillator mode off off 20 mhz 125 khz no division ? ? 5.0 11 ma off off 20 mhz 125 khz divide-by-8 ? ? 2.1 ? ma off off 4 mhz 125 khz divide-by-16 mstcr0 = beh mstcr1 = 3fh ?0.9?ma low- speed on-chip oscillator mode off off off 125 khz no division fmr27 = 1 vca20 = 0 ? 110 320 a off off off 125 khz divide-by-8 fmr27 = 1 vca20 = 0 ?63220 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?60220 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?46? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?9.050 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?2.833 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer rh operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?4.6? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer rh operation in real- time clock mode ?2.4? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?0.52.2 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ?1.2? a power- off mode off off off off ? ? power-off 0 topr = 25 c ? 0.01 0.1 a off off off off ? ? power-off 0 topr = 85 c ?0.03? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 25 c ?1.86.4 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 85 c ?2.7? a r01ds0011ej0100 rev.1.00 page 88 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. this applies when the drive capacity of the output transistor is set to high by registers p7drr and p8drr. when the drive capacity is set to low, the value of any other pin applies. table 5.49 dc characteristics (3) [2.7 v vcc < 4.0 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p7_0, p7_1, p8 (1) i oh = ? 5 ma v cc ? 0.5 ? v cc v other pins i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage port p7_0, p7_1, p8 (1) i ol = 5 ma ? ? 0.5 v other pins i ol = 1 ma ? ? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , trcioa, trciob, trcioc, trciod, trj0io, trj1io, trj2io, trctrg, trcclk, adtrg , rxd0, rxd2, clk0, clk2, ssi, scl, sda, sso 0.05 0.4 ? v reset , wkup0 0.1 0.8?v i ih input ?h? current vi = 3 v, v cc = 3 v ? ? 5.0 a i il input ?l? current vi = 0 v, v cc = 3 v ? ? ? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 3 v 25 80 140 k ? r fxin feedback resistance xin ? 2.0 ? m ? r fxcin feedback resistance xcin ? 14 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r01ds0011ej0100 rev.1.00 page 89 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. vcc = 2.7 v to 4.0 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 3.0 v 4. vlcd = vcc, external division resistors are used for vl3 to vl 1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg39 are selecte d, and segment and common output pins are open. the standard value does not include the current that flows through external division resistors . table 5.50 dc characteristics (4) [2.7 v vcc < 4.0 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max . xin (2) xcin high- speed low- speed i cc power supply current (1) high- speed clock mode 20 mhz off off 125 khz no division ? ? 4.7 10 ma 10 mhz off off 125 khz no division ? ? 2.3 6 ma 20 mhz off off off no division fmr27 = 1 mstcr0 = beh mstcr1 = 3fh flash memory off program operation on ram module standby setting enabled ?2.9?ma 20 mhz off off 125 khz divide-by-8 ? ? 1.8 ? ma 10 mhz off off 125 khz divide-by-8 ? ? 1.0 ? ma high- speed on-chip oscillator mode off off 20 mhz 125 khz no division ? ? 5.0 11 ma off off 20 mhz 125 khz divide-by-8 ? ? 2.1 ? ma off off 10 mhz 125 khz no division ? ? 2.9 ? ma off off 10 mhz 125 khz divide-by-8 ? ? 1.5 ? ma off off 4 mhz 125 khz divide-by-16 mstcr0 = beh mstcr1 = 3fh ?0.9?ma low- speed on-chip oscillator mode off off off 125 khz no division fmr27 = 1 vca20 = 0 ? 106 300 a off off off 125 khz divide-by-8 fmr27 = 1 vca20 = 0 ?54200 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?54200 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?36? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?9.050 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?2.531 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer rh operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?3.1? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer rh operation in real- time clock mode ?1.7? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?0.52.2 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ?1.2? a power- off mode off off off off ? ? power-off 0 topr = 25 c ? 0.01 0.1 a off off off off ? ? power-off 0 topr = 85 c ?0.02? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 25 c ?1.34.5 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 topr = 85 c ?2.2? a r01ds0011ej0100 rev.1.00 page 90 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. this applies when the drive capacity of the output transistor is set to high by registers p7drr and p8drr. when the drive capacity is set to low, the value of any other pin applies. table 5.51 dc characteristics (5) [1.8 v vcc < 2.7 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p7_0, p7_1, p8 (1) i oh = ? 2 ma v cc ? 0.5 ? v cc v other pins i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage port p7_0, p7_1, p8 (1) i ol = 2 ma ? ? 0.5 v other pins i ol = 1 ma ? ? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , trcioa, trciob, trcioc, trciod, trj0io, trj1io, trj2io, trctrg, trcclk, adtrg , rxd0, rxd2, clk0, clk2, ssi, scl, sda, sso 0.05 0.4 ? v reset , wkup0 0.1 0.8 ? v i ih input ?h? current vi = 1.8 v, v cc = 1.8 v ? ? 4.0 a i il input ?l? current vi = 0 v, v cc = 1.8 v ? ? ? 4.0 a r pullup pull-up resistance vi = 0 v, v cc = 1.8 v 85 220 500 k ? r fxin feedback resistance xin ? 2.0 ? m ? r fxcin feedback resistance xcin ? 14 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r01ds0011ej0100 rev.1.00 page 91 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics notes: 1. vcc = 1.8 v to 2.7 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 2.2 v 4. vlcd = vcc, external division resistors are used for vl3 to vl 1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg39 are selecte d, and segment and common output pins are open.the standard value does not includ e the current that flows through external division resistors. table 5.52 dc characteristics (6) [1.8 v vcc < 2.7 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max . xin (2) xcin high- speed low- speed i cc power supply current (1) high- speed clock mode 8 mhz off off 125 khz no division ? ? 2.1 ? ma 8 mhz off off 125 khz divide-by-8 ? ? 0.9 ? ma high- speed on-chip oscillator mode off off 5 mhz 125 khz no division ? ? 1.8 5 ma off off 5 mhz 125 khz divide-by-8 ? ? 1.1 ? ma off off 4 mhz 125 khz divide-by-16 mstcr0 = beh mstcr1 = 3fh ?0.9?ma low- speed on-chip oscillator mode off off off 125 khz no division fmr27 = 1 vca20 = 0 ? 106 300 a off off off 125 khz divide-by-8 fmr27 = 1 vca20 = 0 ?54200 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?54200 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?36? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?9.050 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?2.531 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer rh operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?2.4? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer rh operation in real- time clock mode ?1.7? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 to p r = 2 5 c peripheral clock off ?0.52.2 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 to p r = 8 5 c peripheral clock off ?1.2? a power- off mode off off off off ? ? power-off 0 to p r = 2 5 c ? 0.01 0.1 a off off off off ? ? power-off 0 to p r = 8 5 c ?0.02? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 to p r = 2 5 c ?1.24 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 power-off 2 to p r = 8 5 c ?2? a r01ds0011ej0100 rev.1.00 page 92 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics 5.2.5 ac characteristics note: 1. 1t cyc = 1/f1(s) table 5.53 timing requirements of synchronous serial communication unit (ssu) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ? - t cyc (1) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ? ? 1 t cyc (1) slave ? ? 1 s t fall ssck clock falling time master ? ? 1 t cyc (1) slave ? ? 1 s t su sso, ssi data input setup time 100 ? ? ns t h sso, ssi data input hold time 1 ? ? t cyc (1) t lead scs setup time slave 1t cyc + 50 ? ? ns t lag scs hold time slave 1t cyc + 50 ? ? ns t od sso, ssi data output delay time ? ? 1t cyc + 20 ns t sa ssi slave access time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns r01ds0011ej0100 rev.1.00 page 93 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.15 i/o timing of synchronous serial communication unit (ssu) (master) v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register r01ds0011ej0100 rev.1.00 page 94 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.16 i/o timing of synchronous seri al communication unit (ssu) (slave) v ih or v oh v il or v ol scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register r01ds0011ej0100 rev.1.00 page 95 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.17 i/o timing of synchronous serial co mmunication unit (ssu) (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v il or v ol r01ds0011ej0100 rev.1.00 page 96 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics note: 1. 1t cyc = 1/f1(s) figure 5.18 i/o timing of i 2 c bus interface table 5.54 timing requirements of i 2 c bus interface (1) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (1) ??ns t sclh scl input ?h? width 3t cyc + 300 (1) ??ns t scll scl input ?l? width 5t cyc + 500 (1) ??ns t sf scl, sda input fall time ? ? 300 ns t sp scl, sda input spike pulse rejection time ? ? 1t cyc (1) ns t buf sda input bus-free time 5t cyc (1) ??ns t stah start condition input hold time 3t cyc (1) ??ns t stas retransmit start condition input setup time 3t cyc (1) ??ns t stop stop condition input setup time 3t cyc (1) ??ns t sdas data input setup time 1t cyc + 40 (1) ??ns t sdah data input hold time 10 ? ? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition r01ds0011ej0100 rev.1.00 page 97 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics figure 5.19 external clock input timing diagram figure 5.20 input timing of trjiio table 5.55 external clock input (xin, xcin) (v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(xin) xin input cycle time 200 ? 50 ? 50 ? ns t wh(xin) xin input ?h? width 90 ? 24 ? 24 ? ns t wl(xin) xin input ?l? width 90 ? 24 ? 24 ? ns t c(xcin) xcin input cycle time 20 ? 20 ? 20 ? s t wh(xcin) xcin input ?h? width 10 ? 10 ? 10 ? s t wl(xcin) xcin input ?l? width 10 ? 10 ? 10 ? s table 5.56 timing requirements of trjiio (i = 0 to 2) (v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(trjio) trjiio input cycle time 500 ? 300 ? 100 ? ns t wh(trjio) trjiio input ?h? width 200 ? 120 ? 40 ? ns t wl(trjio) trjiio input ?l? width 200 ? 120 ? 40 ? ns external clock input t wh(xin), t wh(xcin) t c(xin), t c(xcin) t wl(xin), t wl(xcin) trjiio input t c(trjio) t wl(trjio) t wh(trjio) r01ds0011ej0100 rev.1.00 page 98 of 102 dec 21, 2010 r8c/la3a group, r8c/la5a group, r8c/la6a gro up, r8c/LA8A group 5. electrical characteristics i = 0, 2 figure 5.21 input and output timing of serial interface notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.22 input timing of external interrupt int i and key input interrupt kii table 5.57 timing requirements of serial interface (v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(ck) clki input cycle time 800 ? 300 ? 200 ? ns t w(ckh) clki input ?h? width 400 ? 150 ? 100 ? ns t w(ckl) clki input ?l? width 400 ? 150 ? 100 ? ns t d(c-q) txdi output delay time ? 200 ? 80 ? 50 ns t h(c-q) txdi hold time 0?0?0?ns t su(d-c) rxdi input setup time 150 ? 70 ? 50 ? ns t h(c-d) rxdi input hold time 90 ? 90 ? 90 ? ns table 5.58 timing requirements of external interrupt inti (i = 0 to 7) and key input interrupt kii (i = 0 to 7) (v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version) , unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t w(inh) inti input ?h? width, kii input ?h? width 1000 (1) ? 380 (1) ? 250 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 1000 (2) ? 380 (2) ? 250 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0, 2 inti input (i = 0 to 7) t w(inl) t w(inh) kii input (i = 0 to 7) r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group package dimensions r01ds0011ej0100 rev.1.00 page 99 of 102 dec 21, 2010 package dimensions diagrams showing the latest package dimensions and moun ting information are available in the ?p ackages? section of the renesas electronics web site. 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 f 32 25 24 17 16 9 8 1 * 1 * 2 x b p e h e e d h d z d z e detail f l 1 l a c a 2 a 1 previous code jeita package code renesas code plqp0032gb-a 32p6u-a mass[typ.] 0.2g p-lqfp32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section b 1 c 1 bp c y s s r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group package dimensions r01ds0011ej0100 rev.1.00 page 100 of 102 dec 21, 2010 include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. detail f c a l1 l a2 a1 index mark x * 3 * 1 * 2 f 39 27 13 1 40 52 26 14 zd ze d hd e he bp terminal cross section c bp c1 b1 previous code jeita package code renesas code plqp0052ja-a 52p6a-a mass[typ.] 0.3g p-lqfp52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.20 0.145 0.09 0.37 0.32 0.27 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group package dimensions r01ds0011ej0100 rev.1.00 page 101 of 102 dec 21, 2010 terminal cross section b1 c1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. * 3 116 17 32 33 48 49 64 f * 1 * 2 x index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a/ ? mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group package dimensions r01ds0011ej0100 rev.1.00 page 102 of 102 dec 21, 2010 detail f c a l 1 l a 1 a 2 index mark * 2 * 1 * 3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 12.1 12.0 11.9 d 12.1 12.0 11.9 e 1.4 a 2 14.2 14.0 13.8 14.2 14.0 13.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1 y s s l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.65 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.27 0.32 0.37 0.09 0.145 0.20 0.13 0.825 0.825 0.30 0.125 1.0 p-lqfp80-14x14-0.65 0.6g mass[typ.] fp-80w / fp-80wv plqp0080ja-a renesas code jeita package code previous code include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. c 1 c b p b 1 terminal cross section a 2 c l a 1 a l 1 detail f z e z d h e h d d e * 2 * 1 * 3 f 80 61 60 41 40 21 20 1 index mark e b p m s ys r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group datasheet c - 1 rev. date description page summary 0.01 jan 18, 2010 ? first edition issued 0.02 jul 16, 2010 2 table 1.1 revised 3 table 1.2 revised 4 tables 1.4 and 1.5 revised 5 table 1.6 revised 6 table 1.7 revised 7 table 1.8 revised 8 table 1.9 and figure 1.1 revised 9 table 1.10 and figure 1.2 revised 10 table 1.11 and figure 1.3 revised 11 table 1.12 revised 12 figure 1.5 revised 13 figure 1.6 revised 14 figure 1.7 revised 16 figure 1.9 revised 17 figure 1.10 revised 18 table 1.13 revised 19 table 1.14 revised 20 figure 1.11 revised 21 figure 1.12 revised 25 table 1.18 revised 26 table 1.19 revised 30 figure 3.1 revised 31 table 4.1, note 3 revised 35 table 4.5 revised 41 to 44 package dimensions revised 1.00 dec 21, 2010 all ?preliminary? and ?under development? deleted 2 table 1.1 revised 3 tables 1.2 and 1.3 note 2 revised 4 tables 1.4 and 1.5 note 1 revised 6 table 1.7 revised 7 table 1.8 revised 10 table 1.11 and figure 1.3 revised 12 figure 1.5 revised 13 figure 1.6 revised 14 figure 1.7 revised 15 figure 1.8 revised 16 figure 1.9 revised 18 table 1.13 revised 19 table 1.14 revised 20 figure 1.11 revised 22 table 1.15 revised 23 table 1.16 revised 24 table 1.17 revised 25, 26 tables 1.18 and 1.19 pin functions for r8c/la5a group added revision history revision history r8c/la3a group, r8c/la5a group, r8c/la6a group, r8c/LA8A group datasheet c - 2 1.00 dec 21, 2010 32 ?the internal rom (program ro m) is allocated lower addresses, beginning with address 0ffffh.? deleted figure 3.1 revised 33 to 41 tables 4.1 to 4.9 sfr information for r8c/la5a group added 52 to 98 ?5. electrical characteristics? added 92 package dimensions ?pvqn0064lb-a? deleted rev. date description page summary all trademarks and registered trademarks are the property of thei r respective owners. general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2010 renesas electronics corporation. all rights reserved. colophon 1.0 |
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